OV - - Loop 56176 - engine_linuxa64

0x16ff56c LDPSW	W16, W17, [X14], #8    [2]

0x16ff570 LDP	D1, D2, [X10, #1016]    [3]

0x16ff574 ADD	X10, X10, #16

0x16ff578 UBFM	X16, X16, #61, #60

0x16ff57c LDR	D3, [X18, X16]    [4]

0x16ff580 UBFM	X17, X17, #61, #60

0x16ff584 LDR	D4, [X18, X17]    [4]

0x16ff588 FCMP	D3, D0

0x16ff58c FCSEL	D3, D0, D3, #9

0x16ff590 FCMP	D4, D0

0x16ff594 FCSEL	D4, D0, D4, #9

0x16ff598 FDIV	D1, D1, D3

0x16ff59c SUBS	X15, X15, #2

0x16ff5a0 FDIV	D2, D2, D4

0x16ff5a4 STR	D1, [X19, X16]    [1]

0x16ff5a8 STR	D2, [X19, X17]    [1]

0x16ff5ac B.NE	16ff56c

/work/m23012/camus/OpenRadioss/OpenRadioss/engine/source/output/anim/generate/dfuncc.F: 4870 - 4870

--------------------------------------------------------------------------------

4870:                   FUNC(EL2FA(NN4+N)) = EVAR(I)/

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	2.80 - 5.59
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	1.98 - 2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.40 - 2.80
Bottlenecks	P4,
Function	dfuncc
Source	dfuncc.F:4870-4870
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	6.99 - 13.99
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	3.68 - 6.99
CQA cycles if fully vectorized	3.53 - 6.99
Front-end cycles	5.00
P0 cycles	1.00
P1 cycles	2.67
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	4.00
P5 cycles	4.00
P6 cycles	3.00
P7 cycles	3.00
DIV/SQRT cycles	6.99 - 13.99
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.29 - 0.14
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.00 - 8.01
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	16.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	9.09
Vectorization ratio load	33.33
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	54.55
Vector-efficiency ratio load	66.67
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	2.80 - 5.59
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	1.98 - 2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.40 - 2.80
Bottlenecks	P4,
Function	dfuncc
Source	dfuncc.F:4870-4870
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	6.99 - 13.99
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	3.68 - 6.99
CQA cycles if fully vectorized	3.53 - 6.99
Front-end cycles	5.00
P0 cycles	1.00
P1 cycles	2.67
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	4.00
P5 cycles	4.00
P6 cycles	3.00
P7 cycles	3.00
DIV/SQRT cycles	6.99 - 13.99
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.29 - 0.14
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.00 - 8.01
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	16.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	9.09
Vectorization ratio load	33.33
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	54.55
Vector-efficiency ratio load	66.67
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	dfuncc
Source file and lines	dfuncc.F:4870-4870
Module	engine_linuxa64_ompi

The loop is defined in /work/m23012/camus/OpenRadioss/OpenRadioss/engine/source/output/anim/generate/dfuncc.F:4870.

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.99 to 2.50 cycles (5.59x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 54% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 13.99 to 6.99 cycles (2.00x speedup).

Details

9% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

2: divide

The binary loop is loading 40 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

DOES NOT FIT IN UOP CACHE

front end

5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.00	2.67	2.67	2.67	4.00	4.00	3.00	3.00
cycles	1.00	2.67	2.67	2.67	4.00	4.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: ALU
P2: ALU
P3: ALU
P4 (128 bits): VPU, ALU, DIV/SQRT
P5 (128 bits): ALU, VPU
P6 (128 bits): load, store data, store address
P7 (128 bits): load, store data, store address

Cycles executing div or sqrt instructions	6.99-13.99
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.00
Data deps.	1.00
Overall L1	6.99-13.99

Vectorization ratios

INT

all	20%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	9%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.99 cycles. At this rate:

8% of peak load performance is reached (2.86 out of 32.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.14 out of 32.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 16ff56c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
LDPSW W16, W17, [X14], #8	1	0	0.33	0.33	0.33	0	0	0.50	0.50	5	1	N/A
LDP D1, D2, [X10, #1016]	1	0	0.33	0.33	0.33	0	0	0.50	0.50	5	1	vect (100.0%)
ADD X10, X10, #16	1	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
UBFM X16, X16, #61, #60	1	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LDR D3, [X18, X16]	1	0	0.33	0.33	0.33	0	0	0.50	0.50	5	0.50	scal (50.0%)
UBFM X17, X17, #61, #60	1	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LDR D4, [X18, X17]	1	0	0.33	0.33	0.33	0	0	0.50	0.50	5	0.50	scal (50.0%)
FCMP D3, D0	1	0	0	0	0	1	0	0	0	2	1	scal (50.0%)
FCSEL D3, D0, D3, #9	1	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (50.0%)
FCMP D4, D0	1	0	0	0	0	1	0	0	0	2	1	scal (50.0%)
FCSEL D4, D0, D4, #9	1	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (50.0%)
FDIV D1, D1, D3	1	0	0	0	0	1	0	0	0	7-15	3.50-6.99	scal (50.0%)
SUBS X15, X15, #2	1	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
FDIV D2, D2, D4	1	0	0	0	0	1	0	0	0	7-15	3.50-6.99	scal (50.0%)
STR D1, [X19, X16]	1	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	scal (50.0%)
STR D2, [X19, X17]	1	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	scal (50.0%)
B.NE 16ff56c <dfuncc_+0x1958>	1	1	0	0	0	0	0	0	0	1	1	N/A

Function	dfuncc
Source file and lines	dfuncc.F:4870-4870
Module	engine_linuxa64_ompi

The loop is defined in /work/m23012/camus/OpenRadioss/OpenRadioss/engine/source/output/anim/generate/dfuncc.F:4870.

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.99 to 2.50 cycles (5.59x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 54% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 13.99 to 6.99 cycles (2.00x speedup).

Details

9% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

2: divide

The binary loop is loading 40 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

DOES NOT FIT IN UOP CACHE

front end

5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.00	2.67	2.67	2.67	4.00	4.00	3.00	3.00
cycles	1.00	2.67	2.67	2.67	4.00	4.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: ALU
P2: ALU
P3: ALU
P4 (128 bits): VPU, ALU, DIV/SQRT
P5 (128 bits): ALU, VPU
P6 (128 bits): load, store data, store address
P7 (128 bits): load, store data, store address

Cycles executing div or sqrt instructions	6.99-13.99
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.00
Data deps.	1.00
Overall L1	6.99-13.99

Vectorization ratios

INT

all	20%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	9%
load	33%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.99 cycles. At this rate:

8% of peak load performance is reached (2.86 out of 32.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.14 out of 32.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 16ff56c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
LDPSW W16, W17, [X14], #8	1	0	0.33	0.33	0.33	0	0	0.50	0.50	5	1	N/A
LDP D1, D2, [X10, #1016]	1	0	0.33	0.33	0.33	0	0	0.50	0.50	5	1	vect (100.0%)
ADD X10, X10, #16	1	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
UBFM X16, X16, #61, #60	1	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LDR D3, [X18, X16]	1	0	0.33	0.33	0.33	0	0	0.50	0.50	5	0.50	scal (50.0%)
UBFM X17, X17, #61, #60	1	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LDR D4, [X18, X17]	1	0	0.33	0.33	0.33	0	0	0.50	0.50	5	0.50	scal (50.0%)
FCMP D3, D0	1	0	0	0	0	1	0	0	0	2	1	scal (50.0%)
FCSEL D3, D0, D3, #9	1	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (50.0%)
FCMP D4, D0	1	0	0	0	0	1	0	0	0	2	1	scal (50.0%)
FCSEL D4, D0, D4, #9	1	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (50.0%)
FDIV D1, D1, D3	1	0	0	0	0	1	0	0	0	7-15	3.50-6.99	scal (50.0%)
SUBS X15, X15, #2	1	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
FDIV D2, D2, D4	1	0	0	0	0	1	0	0	0	7-15	3.50-6.99	scal (50.0%)
STR D1, [X19, X16]	1	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	scal (50.0%)
STR D2, [X19, X17]	1	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	scal (50.0%)
B.NE 16ff56c <dfuncc_+0x1958>	1	1	0	0	0	0	0	0	0	1	1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code