OV - exec - Function hypre_BoomerAMGCreateS.omp

	Function: hypre_BoomerAMGCreateS.omp_outlined.2	Module: exec	Source: par_strength.c:246-513 [...]	Coverage (incl. loops): 0.29% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 246 - 513

--------------------------------------------------------------------------------

246: #pragma omp parallel private(i,diag,row_scale,row_sum,jA,jS)

247: #endif

248:    {

249:    HYPRE_Int start, stop;

250:    hypre_GetSimpleThreadPartition(&start, &stop, num_variables);

251:    HYPRE_Int jS_diag = 0, jS_offd = 0;

252:

253:    for (i = start; i < stop; i++)

254:    {

255:       S_diag_i[i] = jS_diag;

256:       if (num_cols_offd)

257:       {

258:          S_offd_i[i] = jS_offd;

259:       }

260:

261:       diag = A_diag_data[A_diag_i[i]];

262:

263:       /* compute scaling factor and row sum */

264:       row_scale = 0.0;

265:       row_sum = diag;

266:       if (num_functions > 1)

267:       {

268:          if (diag < 0)

269:          {

270:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

271:             {

272:                if (dof_func[i] == dof_func[A_diag_j[jA]])

273:                {

274:                   row_scale = hypre_max(row_scale, A_diag_data[jA]);

275:                   row_sum += A_diag_data[jA];

276:                }

277:             }

278:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

279:             {

280:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

281:                {

282:                   row_scale = hypre_max(row_scale, A_offd_data[jA]);

283:                   row_sum += A_offd_data[jA];

[...]

289:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

290:             {

291:                if (dof_func[i] == dof_func[A_diag_j[jA]])

292:                {

293:                   row_scale = hypre_min(row_scale, A_diag_data[jA]);

294:                   row_sum += A_diag_data[jA];

295:                }

296:             }

297:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

298:             {

299:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

300:                {

301:                   row_scale = hypre_min(row_scale, A_offd_data[jA]);

302:                   row_sum += A_offd_data[jA];

[...]

309:          if (diag < 0)

310:          {

311:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

312:             {

313:                row_scale = hypre_max(row_scale, A_diag_data[jA]);

314:                row_sum += A_diag_data[jA];

315:             }

316:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

317:             {

318:                row_scale = hypre_max(row_scale, A_offd_data[jA]);

319:                row_sum += A_offd_data[jA];

320:             }

321:          }

322:          else

323:          {

324:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

325:             {

326:                row_scale = hypre_min(row_scale, A_diag_data[jA]);

327:                row_sum += A_diag_data[jA];

328:             }

329:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

330:             {

331:                row_scale = hypre_min(row_scale, A_offd_data[jA]);

332:                row_sum += A_offd_data[jA];

333:             }

334:          } /* diag >= 0*/

335:       } /* num_functions <= 1 */

336:

337:       jS_diag += A_diag_i[i + 1] - A_diag_i[i] - 1;

338:       jS_offd += A_offd_i[i + 1] - A_offd_i[i];

339:

340:       /* compute row entries of S */

341:       S_temp_diag_j[A_diag_i[i]] = -1;

342:       if ((fabs(row_sum) > fabs(diag)*max_row_sum) && (max_row_sum < 1.0))

343:       {

344:          /* make all dependencies weak */

345:          for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

346:          {

347:             S_temp_diag_j[jA] = -1;

348:          }

349:          jS_diag -= A_diag_i[i + 1] - (A_diag_i[i] + 1);

350:

351:          for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

352:          {

353:             S_temp_offd_j[jA] = -1;

354:          }

355:          jS_offd -= A_offd_i[i + 1] - A_offd_i[i];

356:       }

357:       else

358:       {

359:          if (num_functions > 1)

360:          {

361:             if (diag < 0)

362:             {

363:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

364:                {

365:                   if (A_diag_data[jA] <= strength_threshold * row_scale

366:                       || dof_func[i] != dof_func[A_diag_j[jA]])

367:                   {

368:                      S_temp_diag_j[jA] = -1;

369:                      --jS_diag;

370:                   }

371:                   else

372:                   {

373:                      S_temp_diag_j[jA] = A_diag_j[jA];

374:                   }

375:                }

376:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

377:                {

378:                   if (A_offd_data[jA] <= strength_threshold * row_scale

379:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

380:                   {

381:                      S_temp_offd_j[jA] = -1;

382:                      --jS_offd;

383:                   }

384:                   else

385:                   {

386:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

392:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

393:                {

394:                   if (A_diag_data[jA] >= strength_threshold * row_scale

395:                       || dof_func[i] != dof_func[A_diag_j[jA]])

396:                   {

397:                      S_temp_diag_j[jA] = -1;

398:                      --jS_diag;

399:                   }

400:                   else

401:                   {

402:                      S_temp_diag_j[jA] = A_diag_j[jA];

403:                   }

404:                }

405:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

406:                {

407:                   if (A_offd_data[jA] >= strength_threshold * row_scale

408:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

409:                   {

410:                      S_temp_offd_j[jA] = -1;

411:                      --jS_offd;

412:                   }

413:                   else

414:                   {

415:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

422:             if (diag < 0)

423:             {

424:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

425:                {

426:                   if (A_diag_data[jA] <= strength_threshold * row_scale)

427:                   {

428:                      S_temp_diag_j[jA] = -1;

429:                      --jS_diag;

430:                   }

431:                   else

432:                   {

433:                      S_temp_diag_j[jA] = A_diag_j[jA];

434:                   }

435:                }

436:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

437:                {

438:                   if (A_offd_data[jA] <= strength_threshold * row_scale)

439:                   {

440:                      S_temp_offd_j[jA] = -1;

441:                      --jS_offd;

442:                   }

443:                   else

444:                   {

445:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

451:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

452:                {

453:                   if (A_diag_data[jA] >= strength_threshold * row_scale)

454:                   {

455:                      S_temp_diag_j[jA] = -1;

456:                      --jS_diag;

457:                   }

458:                   else

459:                   {

460:                      S_temp_diag_j[jA] = A_diag_j[jA];

461:                   }

462:                }

463:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

464:                {

465:                   if (A_offd_data[jA] >= strength_threshold * row_scale)

466:                   {

467:                      S_temp_offd_j[jA] = -1;

468:                      --jS_offd;

469:                   }

470:                   else

471:                   {

472:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

480:    hypre_prefix_sum_pair(&jS_diag, S_diag_i + num_variables, &jS_offd, S_offd_i + num_variables, prefix_sum_workspace);

[...]

492:    for (i = start; i < stop; i++)

493:    {

494:       S_diag_i[i] += jS_diag;

495:       S_offd_i[i] += jS_offd;

496:

497:       jS = S_diag_i[i];

498:       for (jA = A_diag_i[i]; jA < A_diag_i[i+1]; jA++)

499:       {

500:          if (S_temp_diag_j[jA] > -1)

501:          {

502:             S_diag_j[jS]    = S_temp_diag_j[jA];

503:             jS++;

504:          }

505:       }

506:

507:       jS = S_offd_i[i];

508:       for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

509:       {

510:          if (S_temp_offd_j[jA] > -1)

511:          {

512:             S_offd_j[jS]    = S_temp_offd_j[jA];

513:             jS++;

0x464ec0 SUB	SP, SP, #272

0x464ec4 STP	X29, X30, [SP, #176]

0x464ec8 STP	X28, X27, [SP, #192]

0x464ecc STP	X26, X25, [SP, #208]

0x464ed0 STP	X24, X23, [SP, #224]

0x464ed4 STP	X22, X21, [SP, #240]

0x464ed8 STP	X20, X19, [SP, #256]

0x464edc ADD	X29, SP, #176

0x464ee0 LDR	X8, [X29, #184]

0x464ee4 STR	X2, [SP, #16]

0x464ee8 LDR	X2, [X2]

0x464eec SUB	X0, X29, #16

0x464ef0 SUB	X1, X29, #24

0x464ef4 ORR	X24, XZR, X6

0x464ef8 ORR	X22, XZR, X4

0x464efc ORR	X19, XZR, X3

0x464f00 LDR	X25, [X29, #168]

0x464f04 STR	X7, [SP, #48]

0x464f08 STUR	X5, [X29, #456]

0x464f0c STR	X8, [SP, #24]

0x464f10 LDR	X8, [X29, #152]

0x464f14 STR	X8, [SP, #32]

0x464f18 LDR	X8, [X29, #120]

0x464f1c STR	X8, [SP, #40]

0x464f20 BL	4a8a30

0x464f24 LDP	X9, X12, [X29, #1000]

0x464f28 LDR	X8, [X19]

0x464f2c STP	XZR, XZR, [X29, #984]

0x464f30 STR	X19, [SP, #8]

0x464f34 CMP	X12, X9

0x464f38 B.GE	4659d8

0x464f3c LDP	X13, X3, [X29, #136]

0x464f40 LDR	X5, [X29, #128]

0x464f44 LDR	X11, [X29, #176]

0x464f48 MOVI	D2, #0

0x464f4c FMOV	D3, #1.0000000

0x464f50 MOVN	X26, #0

0x464f54 ORR	X9, XZR, XZR

0x464f58 ORR	X10, XZR, XZR

0x464f5c LDR	X14, [X29, #160]

0x464f60 LDP	X16, X15, [X29, #104]

0x464f64 LDR	X0, [X24]

0x464f68 LDUR	X18, [X29, #456]

0x464f6c LDP	X2, X1, [SP, #40]

0x464f70 LDR	X17, [X29, #96]

0x464f74 LDR	X30, [X25]

0x464f78 STUR	X3, [X29, #464]

0x464f7c LDR	X3, [X3]

0x464f80 STUR	X5, [X29, #448]

0x464f84 LDR	X6, [X5]

0x464f88 LDR	X5, [SP, #32]

0x464f8c LDR	X7, [X15]

0x464f90 LDR	D0, [X14]

0x464f94 LDR	D1, [X11]

0x464f98 ADD	X11, X0, #24

0x464f9c LDR	X19, [X13]

0x464fa0 LDR	X18, [X18]

0x464fa4 LDR	X1, [X1]

0x464fa8 LDR	X2, [X2]

0x464fac LDR	X4, [X16]

0x464fb0 STR	X11, [SP, #88]

0x464fb4 ADD	X11, X3, #16

0x464fb8 LDR	X24, [X5]

0x464fbc STUR	X7, [X29, #440]

0x464fc0 STUR	X19, [X29, #432]

0x464fc4 STR	X11, [SP, #80]

0x464fc8 ADD	X11, X0, #8

0x464fcc STR	X11, [SP, #72]

0x464fd0 ADD	X11, X7, #8

0x464fd4 STR	X11, [SP, #64]

0x464fd8 ADD	X11, X19, #8

0x464fdc STR	X11, [SP, #56]

0x464fe0 B	464ffc

    (2102) 0x464fe4 SUB	X11, X11, X14

    (2102) 0x464fe8 ADD	X9, X11, X9

    (2102) 0x464fec STUR	X9, [X29, #472]

    (2102) 0x464ff0 LDUR	X11, [X29, #488]

    (2102) 0x464ff4 CMP	X12, X11

    (2102) 0x464ff8 B.GE	4659d8

    (2102) 0x464ffc STR	X10, [X8, X12,LSL #3]

    (2102) 0x465000 ORR	X27, XZR, X12

    (2102) 0x465004 LDR	X11, [X22]

    (2102) 0x465008 CBZ	X11, 465010

    (2102) 0x46500c STR	X9, [X18, X27,LSL #3]

    (2102) 0x465010 LDR	X19, [X1, X27,LSL #3]

    (2102) 0x465014 ADD	X12, X27, #1

    (2102) 0x465018 LDR	X11, [X17]

    (2102) 0x46501c MOVI	D5, #0

    (2102) 0x465020 LDR	X28, [X1, X12,LSL #3]

    (2102) 0x465024 LDR	D4, [X0, X19,LSL #3]

    (2102) 0x465028 ADD	X20, X19, #1

    (2102) 0x46502c FMOV	D6, D4

    (2102) 0x465030 CMP	X11, #2

    (2102) 0x465034 B.LT	465088

    (2102) 0x465038 FCMP	D4, #0

    (2102) 0x46503c B.GE	465160

    (2102) 0x465040 CMP	X20, X28

    (2102) 0x465044 B.GE	465284

    (2102) 0x465048 LDR	X21, [X4, X27,LSL #3]

    (2102) 0x46504c MOVI	D5, #0

    (2102) 0x465050 SUB	W11, W19, W28

    (2102) 0x465054 TBNZ	W11, #0, 465274

    (2102) 0x465058 LDUR	X11, [X29, #440]

    (2102) 0x46505c MOVI	D5, #0

    (2102) 0x465060 FMOV	D6, D4

    (2102) 0x465064 LDR	X11, [X11, X20,LSL #3]

    (2102) 0x465068 LDR	X11, [X4, X11,LSL #3]

    (2102) 0x46506c CMP	X21, X11

    (2102) 0x465070 B.NE	465080

    (2102) 0x465074 LDR	D6, [X0, X20,LSL #3]

    (2102) 0x465078 FMAXNM	D5, D6, D2

    (2102) 0x46507c FADD	D6, D6, D4

    (2102) 0x465080 ADD	X20, X19, #2

    (2102) 0x465084 B	465278

    (2102) 0x465088 FCMP	D4, #0

    (2102) 0x46508c B.GE	4651a8

    (2102) 0x465090 CMP	X20, X28

    (2102) 0x465094 B.GE	465134

    (2102) 0x465098 ORN	X11, XZR, X19

    (2102) 0x46509c MOVI	D5, #0

    (2102) 0x4650a0 FMOV	D6, D4

    (2102) 0x4650a4 ADD	X14, X28, X11

    (2102) 0x4650a8 CMP	X14, #4

    (2102) 0x4650ac B.CC	465118

    (2102) 0x4650b0 LDR	X11, [SP, #88]

    (2102) 0x4650b4 AND	X5, X14, #8062

    (2102) 0x4650b8 MOVI	V6.2D, #0

    (2102) 0x4650bc MOV	V6.D[0], V4.D[0]

    (2102) 0x4650c0 MOVI	V5.2D, #0

    (2102) 0x4650c4 MOVI	V7.2D, #0

    (2102) 0x4650c8 MOVI	V16.2D, #0

    (2102) 0x4650cc ADD	X20, X20, X5

    (2102) 0x4650d0 ORR	X21, XZR, X5

    (2102) 0x4650d4 ADD	X7, X11, X19,LSL #3

    (2102) 0x4650d8 HINT	#0

    (2102) 0x4650dc HINT	#0

      (2121) 0x4650e0 LDP	Q17, Q18, [X7, #2032]

      (2121) 0x4650e4 ADD	X7, X7, #32

      (2121) 0x4650e8 SUBS	X21, X21, #4

      (2121) 0x4650ec FMAXNM	V16.2D, V16.2D, V18.2D

      (2121) 0x4650f0 FADD	V5.2D, V18.2D, V5.2D

      (2121) 0x4650f4 FMAXNM	V7.2D, V7.2D, V17.2D

      (2121) 0x4650f8 FADD	V6.2D, V17.2D, V6.2D

      (2121) 0x4650fc B.NE	4650e0

    (2102) 0x465100 FADD	V5.2D, V5.2D, V6.2D

    (2102) 0x465104 FADDP	D6, V5.2D

    (2102) 0x465108 FMAXNM	V5.2D, V7.2D, V16.2D

    (2102) 0x46510c FMAXNMP	D5, V5.2D

    (2102) 0x465110 CMP	X14, X5

    (2102) 0x465114 B.EQ	465134

    (2102) 0x465118 SUB	X11, X28, X20

    (2102) 0x46511c ADD	X14, X0, X20,LSL #3

      (2120) 0x465120 LDR	D7, [X14], #8

      (2120) 0x465124 SUBS	X11, X11, #1

      (2120) 0x465128 FMAXNM	D5, D5, D7

      (2120) 0x46512c FADD	D6, D7, D6

      (2120) 0x465130 B.NE	465120

    (2102) 0x465134 LDR	X21, [X2, X27,LSL #3]

    (2102) 0x465138 LDR	X20, [X2, X12,LSL #3]

    (2102) 0x46513c SUBS	X14, X20, X21

    (2102) 0x465140 B.LE	4655a0

    (2102) 0x465144 CMP	X14, #4

    (2102) 0x465148 B.CS	4652b0

    (2102) 0x46514c ORR	X23, XZR, X21

    (2102) 0x465150 B	465320

0x465154 HINT	#0

0x465158 HINT	#0

0x46515c HINT	#0

    (2102) 0x465160 CMP	X20, X28

    (2102) 0x465164 B.GE	46534c

    (2102) 0x465168 LDR	X21, [X4, X27,LSL #3]

    (2102) 0x46516c MOVI	D5, #0

    (2102) 0x465170 SUB	W11, W19, W28

    (2102) 0x465174 TBNZ	W11, #0, 46533c

    (2102) 0x465178 LDUR	X11, [X29, #440]

    (2102) 0x46517c MOVI	D5, #0

    (2102) 0x465180 FMOV	D6, D4

    (2102) 0x465184 LDR	X11, [X11, X20,LSL #3]

    (2102) 0x465188 LDR	X11, [X4, X11,LSL #3]

    (2102) 0x46518c CMP	X21, X11

    (2102) 0x465190 B.NE	4651a0

    (2102) 0x465194 LDR	D6, [X0, X20,LSL #3]

    (2102) 0x465198 FMINNM	D5, D6, D2

    (2102) 0x46519c FADD	D6, D6, D4

    (2102) 0x4651a0 ADD	X20, X19, #2

    (2102) 0x4651a4 B	465340

    (2102) 0x4651a8 CMP	X20, X28

    (2102) 0x4651ac B.GE	465254

    (2102) 0x4651b0 ORN	X11, XZR, X19

    (2102) 0x4651b4 MOVI	D5, #0

    (2102) 0x4651b8 FMOV	D6, D4

    (2102) 0x4651bc ADD	X14, X28, X11

    (2102) 0x4651c0 CMP	X14, #3

    (2102) 0x4651c4 B.LS	465238

    (2102) 0x4651c8 LDR	X11, [SP, #88]

    (2102) 0x4651cc AND	X5, X14, #8062

    (2102) 0x4651d0 MOVI	V6.2D, #0

    (2102) 0x4651d4 MOV	V6.D[0], V4.D[0]

    (2102) 0x4651d8 MOVI	V5.2D, #0

    (2102) 0x4651dc MOVI	V7.2D, #0

    (2102) 0x4651e0 MOVI	V16.2D, #0

    (2102) 0x4651e4 ADD	X20, X20, X5

    (2102) 0x4651e8 ORR	X21, XZR, X5

    (2102) 0x4651ec ADD	X7, X11, X19,LSL #3

    (2102) 0x4651f0 HINT	#0

    (2102) 0x4651f4 HINT	#0

    (2102) 0x4651f8 HINT	#0

    (2102) 0x4651fc HINT	#0

      (2117) 0x465200 LDP	Q17, Q18, [X7, #2032]

      (2117) 0x465204 ADD	X7, X7, #32

      (2117) 0x465208 SUBS	X21, X21, #4

      (2117) 0x46520c FMINNM	V16.2D, V16.2D, V18.2D

      (2117) 0x465210 FADD	V5.2D, V18.2D, V5.2D

      (2117) 0x465214 FMINNM	V7.2D, V7.2D, V17.2D

      (2117) 0x465218 FADD	V6.2D, V17.2D, V6.2D

      (2117) 0x46521c B.NE	465200

    (2102) 0x465220 FADD	V5.2D, V5.2D, V6.2D

    (2102) 0x465224 FADDP	D6, V5.2D

    (2102) 0x465228 FMINNM	V5.2D, V7.2D, V16.2D

    (2102) 0x46522c FMINNMP	D5, V5.2D

    (2102) 0x465230 CMP	X14, X5

    (2102) 0x465234 B.EQ	465254

    (2102) 0x465238 SUB	X11, X28, X20

    (2102) 0x46523c ADD	X14, X0, X20,LSL #3

      (2116) 0x465240 LDR	D7, [X14], #8

      (2116) 0x465244 SUBS	X11, X11, #1

      (2116) 0x465248 FMINNM	D5, D5, D7

      (2116) 0x46524c FADD	D6, D7, D6

      (2116) 0x465250 B.NE	465240

    (2102) 0x465254 LDR	X21, [X2, X27,LSL #3]

    (2102) 0x465258 LDR	X20, [X2, X12,LSL #3]

    (2102) 0x46525c SUBS	X14, X20, X21

    (2102) 0x465260 B.LE	4655a0

    (2102) 0x465264 CMP	X14, #4

    (2102) 0x465268 B.CS	465378

    (2102) 0x46526c ORR	X23, XZR, X21

    (2102) 0x465270 B	4653e0

    (2102) 0x465274 FMOV	D6, D4

    (2102) 0x465278 SUB	X11, X28, #2

    (2102) 0x46527c CMP	X11, X19

    (2102) 0x465280 B.NE	4653fc

    (2102) 0x465284 LDR	X21, [X2, X27,LSL #3]

    (2102) 0x465288 LDR	X20, [X2, X12,LSL #3]

    (2102) 0x46528c CMP	X20, X21

    (2102) 0x465290 B.LE	4655a0

    (2102) 0x465294 LDUR	X11, [X29, #464]

    (2102) 0x465298 LDR	X23, [X4, X27,LSL #3]

    (2102) 0x46529c LDR	X5, [X11]

    (2102) 0x4652a0 SUB	W11, W20, W21

    (2102) 0x4652a4 TBNZ	W11, #0, 46546c

    (2102) 0x4652a8 ORR	X11, XZR, X21

    (2102) 0x4652ac B	465490

    (2102) 0x4652b0 LDR	X5, [SP, #80]

    (2102) 0x4652b4 DUP	V5.2D, V5.D[0]

    (2102) 0x4652b8 AND	X11, X14, #8062

    (2102) 0x4652bc MOVI	V16.2D, #0

    (2102) 0x4652c0 MOV	V16.D[0], V6.D[0]

    (2102) 0x4652c4 MOVI	V7.2D, #0

    (2102) 0x4652c8 ADD	X23, X21, X11

    (2102) 0x4652cc ORR	V17.16B, V5.16B, V5.16B

    (2102) 0x4652d0 ADD	X7, X5, X21,LSL #3

    (2102) 0x4652d4 ORR	X5, XZR, X11

    (2102) 0x4652d8 HINT	#0

    (2102) 0x4652dc HINT	#0

      (2118) 0x4652e0 LDP	Q6, Q18, [X7, #2032]

      (2118) 0x4652e4 ADD	X7, X7, #32

      (2118) 0x4652e8 SUBS	X5, X5, #4

      (2118) 0x4652ec FMAXNM	V17.2D, V17.2D, V18.2D

      (2118) 0x4652f0 FADD	V7.2D, V18.2D, V7.2D

      (2118) 0x4652f4 FMAXNM	V5.2D, V5.2D, V6.2D

      (2118) 0x4652f8 FADD	V16.2D, V6.2D, V16.2D

      (2118) 0x4652fc B.NE	4652e0

    (2102) 0x465300 FADD	V6.2D, V7.2D, V16.2D

    (2102) 0x465304 FMAXNM	V5.2D, V5.2D, V17.2D

    (2102) 0x465308 FADDP	D6, V6.2D

    (2102) 0x46530c FMAXNMP	D5, V5.2D

    (2102) 0x465310 CMP	X14, X11

    (2102) 0x465314 B.EQ	4655a0

    (2102) 0x465318 HINT	#0

    (2102) 0x46531c HINT	#0

      (2119) 0x465320 LDR	D7, [X3, X23,LSL #3]

      (2119) 0x465324 ADD	X23, X23, #1

      (2119) 0x465328 FMAXNM	D5, D5, D7

      (2119) 0x46532c FADD	D6, D7, D6

      (2119) 0x465330 CMP	X20, X23

      (2119) 0x465334 B.NE	465320

    (2102) 0x465338 B	4655a0

    (2102) 0x46533c FMOV	D6, D4

    (2102) 0x465340 SUB	X11, X28, #2

    (2102) 0x465344 CMP	X11, X19

    (2102) 0x465348 B.NE	46550c

    (2102) 0x46534c LDR	X21, [X2, X27,LSL #3]

    (2102) 0x465350 LDR	X20, [X2, X12,LSL #3]

    (2102) 0x465354 CMP	X20, X21

    (2102) 0x465358 B.LE	4655a0

    (2102) 0x46535c LDUR	X11, [X29, #464]

    (2102) 0x465360 LDR	X23, [X4, X27,LSL #3]

    (2102) 0x465364 LDR	X5, [X11]

    (2102) 0x465368 SUB	W11, W20, W21

    (2102) 0x46536c TBNZ	W11, #0, 465570

    (2102) 0x465370 ORR	X11, XZR, X21

    (2102) 0x465374 B	465594

    (2102) 0x465378 LDR	X11, [SP, #80]

    (2102) 0x46537c DUP	V5.2D, V5.D[0]

    (2102) 0x465380 AND	X5, X14, #8062

    (2102) 0x465384 MOVI	V16.2D, #0

    (2102) 0x465388 MOV	V16.D[0], V6.D[0]

    (2102) 0x46538c MOVI	V7.2D, #0

    (2102) 0x465390 ADD	X23, X21, X5

    (2102) 0x465394 ORR	V17.16B, V5.16B, V5.16B

    (2102) 0x465398 ADD	X7, X11, X21,LSL #3

    (2102) 0x46539c ORR	X11, XZR, X5

      (2114) 0x4653a0 LDP	Q6, Q18, [X7, #2032]

      (2114) 0x4653a4 ADD	X7, X7, #32

      (2114) 0x4653a8 SUBS	X11, X11, #4

      (2114) 0x4653ac FMINNM	V17.2D, V17.2D, V18.2D

      (2114) 0x4653b0 FADD	V7.2D, V18.2D, V7.2D

      (2114) 0x4653b4 FMINNM	V5.2D, V5.2D, V6.2D

      (2114) 0x4653b8 FADD	V16.2D, V6.2D, V16.2D

      (2114) 0x4653bc B.NE	4653a0

    (2102) 0x4653c0 FADD	V6.2D, V7.2D, V16.2D

    (2102) 0x4653c4 FMINNM	V5.2D, V5.2D, V17.2D

    (2102) 0x4653c8 FADDP	D6, V6.2D

    (2102) 0x4653cc FMINNMP	D5, V5.2D

    (2102) 0x4653d0 CMP	X14, X5

    (2102) 0x4653d4 B.EQ	4655a0

    (2102) 0x4653d8 HINT	#0

    (2102) 0x4653dc HINT	#0

      (2115) 0x4653e0 LDR	D7, [X3, X23,LSL #3]

      (2115) 0x4653e4 ADD	X23, X23, #1

      (2115) 0x4653e8 FMINNM	D5, D5, D7

      (2115) 0x4653ec FADD	D6, D7, D6

      (2115) 0x4653f0 CMP	X20, X23

      (2115) 0x4653f4 B.NE	4653e0

    (2102) 0x4653f8 B	4655a0

    (2102) 0x4653fc LDR	X11, [SP, #72]

    (2102) 0x465400 SUB	X23, X28, X20

    (2102) 0x465404 ADD	X14, X11, X20,LSL #3

    (2102) 0x465408 LDR	X11, [SP, #64]

    (2102) 0x46540c ADD	X20, X11, X20,LSL #3

    (2102) 0x465410 B	465430

0x465414 HINT	#0

0x465418 HINT	#0

0x46541c HINT	#0

      (2125) 0x465420 ADD	X20, X20, #16

      (2125) 0x465424 SUBS	X23, X23, #2

      (2125) 0x465428 ADD	X14, X14, #16

      (2125) 0x46542c B.EQ	465284

      (2125) 0x465430 LDUR	X11, [X20, #504]

      (2125) 0x465434 LDR	X11, [X4, X11,LSL #3]

      (2125) 0x465438 CMP	X21, X11

      (2125) 0x46543c B.NE	46544c

      (2125) 0x465440 LDUR	D7, [X14, #504]

      (2125) 0x465444 FMAXNM	D5, D5, D7

      (2125) 0x465448 FADD	D6, D7, D6

      (2125) 0x46544c LDR	X11, [X20]

      (2125) 0x465450 LDR	X11, [X4, X11,LSL #3]

      (2125) 0x465454 CMP	X21, X11

      (2125) 0x465458 B.NE	465420

      (2125) 0x46545c LDR	D7, [X14]

      (2125) 0x465460 FMAXNM	D5, D5, D7

      (2125) 0x465464 FADD	D6, D7, D6

      (2125) 0x465468 B	465420

    (2102) 0x46546c LDUR	X11, [X29, #432]

    (2102) 0x465470 LDR	X11, [X11, X21,LSL #3]

    (2102) 0x465474 LDR	X11, [X6, X11,LSL #3]

    (2102) 0x465478 CMP	X23, X11

    (2102) 0x46547c B.NE	46548c

    (2102) 0x465480 LDR	D7, [X5, X21,LSL #3]

    (2102) 0x465484 FMAXNM	D5, D5, D7

    (2102) 0x465488 FADD	D6, D7, D6

    (2102) 0x46548c ADD	X11, X21, #1

    (2102) 0x465490 ADD	X14, X21, #1

    (2102) 0x465494 CMP	X20, X14

    (2102) 0x465498 B.EQ	4655a0

    (2102) 0x46549c LDR	X7, [SP, #56]

    (2102) 0x4654a0 ADD	X5, X5, X11,LSL #3

    (2102) 0x4654a4 SUB	X14, X20, X11

    (2102) 0x4654a8 ADD	X5, X5, #8

    (2102) 0x4654ac ADD	X7, X7, X11,LSL #3

    (2102) 0x4654b0 B	4654d0

0x4654b4 HINT	#0

0x4654b8 HINT	#0

0x4654bc HINT	#0

      (2124) 0x4654c0 SUBS	X14, X14, #2

      (2124) 0x4654c4 ADD	X5, X5, #16

      (2124) 0x4654c8 ADD	X7, X7, #16

      (2124) 0x4654cc B.EQ	4655a0

      (2124) 0x4654d0 LDUR	X11, [X7, #504]

      (2124) 0x4654d4 LDR	X11, [X6, X11,LSL #3]

      (2124) 0x4654d8 CMP	X23, X11

      (2124) 0x4654dc B.NE	4654ec

      (2124) 0x4654e0 LDUR	D7, [X5, #504]

      (2124) 0x4654e4 FMAXNM	D5, D5, D7

      (2124) 0x4654e8 FADD	D6, D7, D6

      (2124) 0x4654ec LDR	X11, [X7]

      (2124) 0x4654f0 LDR	X11, [X6, X11,LSL #3]

      (2124) 0x4654f4 CMP	X23, X11

      (2124) 0x4654f8 B.NE	4654c0

      (2124) 0x4654fc LDR	D7, [X5]

      (2124) 0x465500 FMAXNM	D5, D5, D7

      (2124) 0x465504 FADD	D6, D7, D6

      (2124) 0x465508 B	4654c0

    (2102) 0x46550c LDR	X11, [SP, #72]

    (2102) 0x465510 SUB	X23, X28, X20

    (2102) 0x465514 ADD	X14, X11, X20,LSL #3

    (2102) 0x465518 LDR	X11, [SP, #64]

    (2102) 0x46551c ADD	X20, X11, X20,LSL #3

    (2102) 0x465520 B	465534

      (2123) 0x465524 ADD	X20, X20, #16

      (2123) 0x465528 SUBS	X23, X23, #2

      (2123) 0x46552c ADD	X14, X14, #16

      (2123) 0x465530 B.EQ	46534c

      (2123) 0x465534 LDUR	X11, [X20, #504]

      (2123) 0x465538 LDR	X11, [X4, X11,LSL #3]

      (2123) 0x46553c CMP	X21, X11

      (2123) 0x465540 B.NE	465550

      (2123) 0x465544 LDUR	D7, [X14, #504]

      (2123) 0x465548 FMINNM	D5, D5, D7

      (2123) 0x46554c FADD	D6, D7, D6

      (2123) 0x465550 LDR	X11, [X20]

      (2123) 0x465554 LDR	X11, [X4, X11,LSL #3]

      (2123) 0x465558 CMP	X21, X11

      (2123) 0x46555c B.NE	465524

      (2123) 0x465560 LDR	D7, [X14]

      (2123) 0x465564 FMINNM	D5, D5, D7

      (2123) 0x465568 FADD	D6, D7, D6

      (2123) 0x46556c B	465524

    (2102) 0x465570 LDUR	X11, [X29, #432]

    (2102) 0x465574 LDR	X11, [X11, X21,LSL #3]

    (2102) 0x465578 LDR	X11, [X6, X11,LSL #3]

    (2102) 0x46557c CMP	X23, X11

    (2102) 0x465580 B.NE	465590

    (2102) 0x465584 LDR	D7, [X5, X21,LSL #3]

    (2102) 0x465588 FMINNM	D5, D5, D7

    (2102) 0x46558c FADD	D6, D7, D6

    (2102) 0x465590 ADD	X11, X21, #1

    (2102) 0x465594 ADD	X14, X21, #1

    (2102) 0x465598 CMP	X20, X14

    (2102) 0x46559c B.NE	465974

    (2102) 0x4655a0 FABS	D7, D4

    (2102) 0x4655a4 FABS	D6, D6

    (2102) 0x4655a8 ORN	X11, XZR, X19

    (2102) 0x4655ac ADD	X10, X28, X10

    (2102) 0x4655b0 ADD	X10, X10, X11

    (2102) 0x4655b4 SUB	X11, X20, X21

    (2102) 0x4655b8 FMUL	D7, D0, D7

    (2102) 0x4655bc ADD	X9, X11, X9

    (2102) 0x4655c0 STP	X9, X10, [X29, #984]

    (2102) 0x4655c4 STR	X26, [X24, X19,LSL #3]

    (2102) 0x4655c8 FCMP	D6, D7

    (2102) 0x4655cc FCCMP	D0, D3, #0, #12

    (2102) 0x4655d0 B.LT	465660

    (2102) 0x4655d4 LDR	X11, [X1, X27,LSL #3]

    (2102) 0x4655d8 LDR	X14, [X17]

    (2102) 0x4655dc ADD	X19, X11, #1

    (2102) 0x4655e0 LDR	X11, [X1, X12,LSL #3]

    (2102) 0x4655e4 CMP	X14, #2

    (2102) 0x4655e8 B.LT	4656e0

    (2102) 0x4655ec FCMP	D4, #0

    (2102) 0x4655f0 B.GE	465734

    (2102) 0x4655f4 CMP	X19, X11

    (2102) 0x4655f8 B.GE	465790

    (2102) 0x4655fc LDR	X14, [X16]

    (2102) 0x465600 LDR	X5, [X15]

    (2102) 0x465604 FMUL	D4, D1, D5

    (2102) 0x465608 B	465628

      (2113) 0x46560c SUB	X10, X10, #1

      (2113) 0x465610 STR	X26, [X24, X19,LSL #3]

      (2113) 0x465614 STUR	X10, [X29, #480]

      (2113) 0x465618 LDR	X11, [X1, X12,LSL #3]

      (2113) 0x46561c ADD	X19, X19, #1

      (2113) 0x465620 CMP	X19, X11

      (2113) 0x465624 B.GE	465790

      (2113) 0x465628 LDR	D6, [X0, X19,LSL #3]

      (2113) 0x46562c FCMP	D6, D4

      (2113) 0x465630 B.LE	46560c

      (2113) 0x465634 LDR	X11, [X5, X19,LSL #3]

      (2113) 0x465638 LDR	X7, [X14, X27,LSL #3]

      (2113) 0x46563c LDR	X20, [X14, X11,LSL #3]

      (2113) 0x465640 CMP	X7, X20

      (2113) 0x465644 B.NE	46560c

      (2113) 0x465648 STR	X11, [X24, X19,LSL #3]

      (2113) 0x46564c B	465618

0x465650 HINT	#0

0x465654 HINT	#0

0x465658 HINT	#0

0x46565c HINT	#0

    (2102) 0x465660 LDR	X11, [X1, X27,LSL #3]

    (2102) 0x465664 LDR	X14, [X1, X12,LSL #3]

    (2102) 0x465668 ADD	X11, X11, #1

    (2102) 0x46566c CMP	X11, X14

    (2102) 0x465670 B.GE	46569c

    (2102) 0x465674 HINT	#0

    (2102) 0x465678 HINT	#0

    (2102) 0x46567c HINT	#0

      (2104) 0x465680 STR	X26, [X24, X11,LSL #3]

      (2104) 0x465684 ADD	X11, X11, #1

      (2104) 0x465688 LDR	X14, [X1, X12,LSL #3]

      (2104) 0x46568c CMP	X11, X14

      (2104) 0x465690 B.LT	465680

    (2102) 0x465694 LDR	X11, [X1, X27,LSL #3]

    (2102) 0x465698 ADD	X11, X11, #1

    (2102) 0x46569c SUB	X11, X11, X14

    (2102) 0x4656a0 ADD	X10, X11, X10

    (2102) 0x4656a4 STUR	X10, [X29, #480]

    (2102) 0x4656a8 LDR	X11, [X2, X27,LSL #3]

    (2102) 0x4656ac LDR	X14, [X2, X12,LSL #3]

    (2102) 0x4656b0 CMP	X11, X14

    (2102) 0x4656b4 B.GE	464fe4

    (2102) 0x4656b8 HINT	#0

    (2102) 0x4656bc HINT	#0

      (2103) 0x4656c0 STR	X26, [X30, X11,LSL #3]

      (2103) 0x4656c4 ADD	X11, X11, #1

      (2103) 0x4656c8 LDR	X14, [X2, X12,LSL #3]

      (2103) 0x4656cc CMP	X11, X14

      (2103) 0x4656d0 B.LT	4656c0

    (2102) 0x4656d4 LDR	X11, [X2, X27,LSL #3]

    (2102) 0x4656d8 B	464fe4

0x4656dc HINT	#0

    (2102) 0x4656e0 FCMP	D4, #0

    (2102) 0x4656e4 B.GE	465804

    (2102) 0x4656e8 CMP	X19, X11

    (2102) 0x4656ec B.GE	465854

    (2102) 0x4656f0 LDR	X14, [X15]

    (2102) 0x4656f4 FMUL	D4, D1, D5

    (2102) 0x4656f8 B	465718

0x4656fc HINT	#0

      (2109) 0x465700 LDR	X11, [X14, X19,LSL #3]

      (2109) 0x465704 STR	X11, [X24, X19,LSL #3]

      (2109) 0x465708 LDR	X11, [X1, X12,LSL #3]

      (2109) 0x46570c ADD	X19, X19, #1

      (2109) 0x465710 CMP	X19, X11

      (2109) 0x465714 B.GE	465854

      (2109) 0x465718 LDR	D6, [X0, X19,LSL #3]

      (2109) 0x46571c FCMP	D6, D4

      (2109) 0x465720 B.GT	465700

      (2109) 0x465724 SUB	X10, X10, #1

      (2109) 0x465728 STR	X26, [X24, X19,LSL #3]

      (2109) 0x46572c STUR	X10, [X29, #480]

      (2109) 0x465730 B	465708

    (2102) 0x465734 CMP	X19, X11

    (2102) 0x465738 B.GE	4658b4

    (2102) 0x46573c LDR	X14, [X16]

    (2102) 0x465740 LDR	X5, [X15]

    (2102) 0x465744 FMUL	D4, D1, D5

    (2102) 0x465748 B	465768

      (2111) 0x46574c SUB	X10, X10, #1

      (2111) 0x465750 STR	X26, [X24, X19,LSL #3]

      (2111) 0x465754 STUR	X10, [X29, #480]

      (2111) 0x465758 LDR	X11, [X1, X12,LSL #3]

      (2111) 0x46575c ADD	X19, X19, #1

      (2111) 0x465760 CMP	X19, X11

      (2111) 0x465764 B.GE	4658b4

      (2111) 0x465768 LDR	D6, [X0, X19,LSL #3]

      (2111) 0x46576c FCMP	D6, D4

      (2111) 0x465770 B.GE	46574c

      (2111) 0x465774 LDR	X11, [X5, X19,LSL #3]

      (2111) 0x465778 LDR	X7, [X14, X27,LSL #3]

      (2111) 0x46577c LDR	X20, [X14, X11,LSL #3]

      (2111) 0x465780 CMP	X7, X20

      (2111) 0x465784 B.NE	46574c

      (2111) 0x465788 STR	X11, [X24, X19,LSL #3]

      (2111) 0x46578c B	465758

    (2102) 0x465790 LDR	X14, [X2, X27,LSL #3]

    (2102) 0x465794 LDR	X11, [X2, X12,LSL #3]

    (2102) 0x465798 CMP	X14, X11

    (2102) 0x46579c B.GE	464ff0

    (2102) 0x4657a0 LDUR	X11, [X29, #448]

    (2102) 0x4657a4 LDR	X5, [X16]

    (2102) 0x4657a8 LDR	X19, [X13]

    (2102) 0x4657ac FMUL	D4, D1, D5

    (2102) 0x4657b0 LDR	X20, [X25]

    (2102) 0x4657b4 LDR	X7, [X11]

    (2102) 0x4657b8 B	4657dc

0x4657bc HINT	#0

      (2112) 0x4657c0 SUB	X9, X9, #1

      (2112) 0x4657c4 STR	X26, [X20, X14,LSL #3]

      (2112) 0x4657c8 STUR	X9, [X29, #472]

      (2112) 0x4657cc LDR	X11, [X2, X12,LSL #3]

      (2112) 0x4657d0 ADD	X14, X14, #1

      (2112) 0x4657d4 CMP	X14, X11

      (2112) 0x4657d8 B.GE	464ff0

      (2112) 0x4657dc LDR	D5, [X3, X14,LSL #3]

      (2112) 0x4657e0 FCMP	D5, D4

      (2112) 0x4657e4 B.LE	4657c0

      (2112) 0x4657e8 LDR	X11, [X19, X14,LSL #3]

      (2112) 0x4657ec LDR	X21, [X5, X27,LSL #3]

      (2112) 0x4657f0 LDR	X23, [X7, X11,LSL #3]

      (2112) 0x4657f4 CMP	X21, X23

      (2112) 0x4657f8 B.NE	4657c0

      (2112) 0x4657fc STR	X11, [X20, X14,LSL #3]

      (2112) 0x465800 B	4657cc

    (2102) 0x465804 FMUL	D4, D1, D5

    (2102) 0x465808 CMP	X19, X11

    (2102) 0x46580c B.GE	465924

    (2102) 0x465810 LDR	X14, [X15]

    (2102) 0x465814 B	465838

0x465818 HINT	#0

0x46581c HINT	#0

      (2106) 0x465820 LDR	X11, [X14, X19,LSL #3]

      (2106) 0x465824 STR	X11, [X24, X19,LSL #3]

      (2106) 0x465828 LDR	X11, [X1, X12,LSL #3]

      (2106) 0x46582c ADD	X19, X19, #1

      (2106) 0x465830 CMP	X19, X11

      (2106) 0x465834 B.GE	465924

      (2106) 0x465838 LDR	D5, [X0, X19,LSL #3]

      (2106) 0x46583c FCMP	D5, D4

      (2106) 0x465840 B.LT	465820

      (2106) 0x465844 SUB	X10, X10, #1

      (2106) 0x465848 STR	X26, [X24, X19,LSL #3]

      (2106) 0x46584c STUR	X10, [X29, #480]

      (2106) 0x465850 B	465828

    (2102) 0x465854 LDR	X14, [X2, X27,LSL #3]

    (2102) 0x465858 LDR	X11, [X2, X12,LSL #3]

    (2102) 0x46585c CMP	X14, X11

    (2102) 0x465860 B.GE	464ff0

  (2108) 0x465864 LDR	X5, [X25]

  (2108) 0x465868 LDR	X7, [X13]

  (2108) 0x46586c FMUL	D4, D1, D5

  (2108) 0x465870 B	465898

0x465874 HINT	#0

0x465878 HINT	#0

0x46587c HINT	#0

(2107) 0x465880 LDR	X11, [X7, X14,LSL #3]

(2107) 0x465884 STR	X11, [X5, X14,LSL #3]

  (2108) 0x465888 LDR	X11, [X2, X12,LSL #3]

  (2108) 0x46588c ADD	X14, X14, #1

  (2108) 0x465890 CMP	X14, X11

  (2108) 0x465894 B.GE	464ff0

  (2108) 0x465898 LDR	D5, [X3, X14,LSL #3]

  (2108) 0x46589c FCMP	D5, D4

  (2108) 0x4658a0 B.GT	465880

  (2108) 0x4658a4 SUB	X9, X9, #1

  (2108) 0x4658a8 STR	X26, [X5, X14,LSL #3]

  (2108) 0x4658ac STUR	X9, [X29, #472]

  (2108) 0x4658b0 B	465888

    (2102) 0x4658b4 LDR	X14, [X2, X27,LSL #3]

    (2102) 0x4658b8 LDR	X11, [X2, X12,LSL #3]

    (2102) 0x4658bc CMP	X14, X11

    (2102) 0x4658c0 B.GE	464ff0

    (2102) 0x4658c4 LDUR	X11, [X29, #448]

    (2102) 0x4658c8 LDR	X5, [X16]

    (2102) 0x4658cc LDR	X19, [X13]

    (2102) 0x4658d0 FMUL	D4, D1, D5

    (2102) 0x4658d4 LDR	X20, [X25]

    (2102) 0x4658d8 LDR	X7, [X11]

    (2102) 0x4658dc B	4658fc

      (2110) 0x4658e0 SUB	X9, X9, #1

      (2110) 0x4658e4 STR	X26, [X20, X14,LSL #3]

      (2110) 0x4658e8 STUR	X9, [X29, #472]

      (2110) 0x4658ec LDR	X11, [X2, X12,LSL #3]

      (2110) 0x4658f0 ADD	X14, X14, #1

      (2110) 0x4658f4 CMP	X14, X11

      (2110) 0x4658f8 B.GE	464ff0

      (2110) 0x4658fc LDR	D5, [X3, X14,LSL #3]

      (2110) 0x465900 FCMP	D5, D4

      (2110) 0x465904 B.GE	4658e0

      (2110) 0x465908 LDR	X11, [X19, X14,LSL #3]

      (2110) 0x46590c LDR	X21, [X5, X27,LSL #3]

      (2110) 0x465910 LDR	X23, [X7, X11,LSL #3]

      (2110) 0x465914 CMP	X21, X23

      (2110) 0x465918 B.NE	4658e0

      (2110) 0x46591c STR	X11, [X20, X14,LSL #3]

      (2110) 0x465920 B	4658ec

    (2102) 0x465924 LDR	X14, [X2, X27,LSL #3]

    (2102) 0x465928 LDR	X11, [X2, X12,LSL #3]

    (2102) 0x46592c CMP	X14, X11

    (2102) 0x465930 B.GE	464ff0

    (2102) 0x465934 LDR	X5, [X25]

    (2102) 0x465938 LDR	X7, [X13]

    (2102) 0x46593c B	465958

      (2105) 0x465940 LDR	X11, [X7, X14,LSL #3]

      (2105) 0x465944 STR	X11, [X5, X14,LSL #3]

      (2105) 0x465948 LDR	X11, [X2, X12,LSL #3]

      (2105) 0x46594c ADD	X14, X14, #1

      (2105) 0x465950 CMP	X14, X11

      (2105) 0x465954 B.GE	464ff0

      (2105) 0x465958 LDR	D5, [X3, X14,LSL #3]

      (2105) 0x46595c FCMP	D5, D4

      (2105) 0x465960 B.LT	465940

      (2105) 0x465964 SUB	X9, X9, #1

      (2105) 0x465968 STR	X26, [X5, X14,LSL #3]

      (2105) 0x46596c STUR	X9, [X29, #472]

      (2105) 0x465970 B	465948

    (2102) 0x465974 LDR	X7, [SP, #56]

    (2102) 0x465978 ADD	X5, X5, X11,LSL #3

    (2102) 0x46597c SUB	X14, X20, X11

    (2102) 0x465980 ADD	X5, X5, #8

    (2102) 0x465984 ADD	X7, X7, X11,LSL #3

    (2102) 0x465988 B	46599c

      (2122) 0x46598c SUBS	X14, X14, #2

      (2122) 0x465990 ADD	X5, X5, #16

      (2122) 0x465994 ADD	X7, X7, #16

      (2122) 0x465998 B.EQ	4655a0

      (2122) 0x46599c LDUR	X11, [X7, #504]

      (2122) 0x4659a0 LDR	X11, [X6, X11,LSL #3]

      (2122) 0x4659a4 CMP	X23, X11

      (2122) 0x4659a8 B.NE	4659b8

      (2122) 0x4659ac LDUR	D7, [X5, #504]

      (2122) 0x4659b0 FMINNM	D5, D5, D7

      (2122) 0x4659b4 FADD	D6, D7, D6

      (2122) 0x4659b8 LDR	X11, [X7]

      (2122) 0x4659bc LDR	X11, [X6, X11,LSL #3]

      (2122) 0x4659c0 CMP	X23, X11

      (2122) 0x4659c4 B.NE	46598c

      (2122) 0x4659c8 LDR	D7, [X5]

      (2122) 0x4659cc FMINNM	D5, D5, D7

      (2122) 0x4659d0 FADD	D6, D7, D6

      (2122) 0x4659d4 B	46598c

0x4659d8 LDP	X9, X11, [SP, #16]

0x4659dc LDUR	X19, [X29, #456]

0x4659e0 SUB	X0, X29, #32

0x4659e4 SUB	X2, X29, #40

0x4659e8 LDR	X9, [X9]

0x4659ec LDR	X10, [X19]

0x4659f0 LDR	X4, [X11]

0x4659f4 ADD	X1, X8, X9,LSL #3

0x4659f8 ADD	X3, X10, X9,LSL #3

0x4659fc BL	4a95f0

0x465a00 LDP	X8, X10, [X29, #1000]

0x465a04 CMP	X10, X8

0x465a08 B.GE	465b04

0x465a0c LDR	X11, [SP, #8]

0x465a10 LDP	X15, X13, [SP, #40]

0x465a14 LDR	X14, [SP, #32]

0x465a18 LDP	X9, X8, [X29, #192]

0x465a1c LDR	X12, [X19]

0x465a20 LDR	X16, [X25]

0x465a24 LDR	X11, [X11]

0x465a28 LDR	X13, [X13]

0x465a2c LDR	X14, [X14]

0x465a30 LDR	X15, [X15]

0x465a34 B	465a4c

0x465a38 HINT	#0

0x465a3c HINT	#0

  (2099) 0x465a40 LDUR	X17, [X29, #488]

  (2099) 0x465a44 CMP	X10, X17

  (2099) 0x465a48 B.GE	465b04

  (2099) 0x465a4c ORR	X17, XZR, X10

  (2099) 0x465a50 LDUR	X10, [X29, #480]

  (2099) 0x465a54 LDR	X18, [X11, X17,LSL #3]

  (2099) 0x465a58 ADD	X10, X18, X10

  (2099) 0x465a5c STR	X10, [X11, X17,LSL #3]

  (2099) 0x465a60 LDUR	X10, [X29, #472]

  (2099) 0x465a64 LDR	X18, [X12, X17,LSL #3]

  (2099) 0x465a68 ADD	X10, X18, X10

  (2099) 0x465a6c STR	X10, [X12, X17,LSL #3]

  (2099) 0x465a70 ADD	X10, X17, #1

  (2099) 0x465a74 LDR	X18, [X13, X17,LSL #3]

  (2099) 0x465a78 LDR	X0, [X13, X10,LSL #3]

  (2099) 0x465a7c CMP	X18, X0

  (2099) 0x465a80 B.GE	465ac4

(2100) 0x465a84 LDR	X1, [X11, X17,LSL #3]

(2100) 0x465a88 LDR	X2, [X9]

(2100) 0x465a8c B	465aac

0x465a90 HINT	#0

0x465a94 HINT	#0

0x465a98 HINT	#0

0x465a9c HINT	#0

(2100) 0x465aa0 ADD	X18, X18, #1

(2100) 0x465aa4 CMP	X18, X0

(2100) 0x465aa8 B.GE	465ac4

(2100) 0x465aac LDR	X3, [X14, X18,LSL #3]

(2100) 0x465ab0 TBNZ	X3, #63, 465aa0

(2100) 0x465ab4 STR	X3, [X2, X1,LSL #3]

(2100) 0x465ab8 ADD	X1, X1, #1

(2100) 0x465abc LDR	X0, [X13, X10,LSL #3]

(2100) 0x465ac0 B	465aa0

  (2099) 0x465ac4 LDR	X18, [X15, X17,LSL #3]

  (2099) 0x465ac8 LDR	X0, [X15, X10,LSL #3]

  (2099) 0x465acc CMP	X18, X0

  (2099) 0x465ad0 B.GE	465a40

  (2099) 0x465ad4 LDR	X17, [X12, X17,LSL #3]

  (2099) 0x465ad8 LDR	X1, [X8]

  (2099) 0x465adc B	465aec

    (2101) 0x465ae0 ADD	X18, X18, #1

    (2101) 0x465ae4 CMP	X18, X0

    (2101) 0x465ae8 B.GE	465a40

    (2101) 0x465aec LDR	X2, [X16, X18,LSL #3]

    (2101) 0x465af0 TBNZ	X2, #63, 465ae0

    (2101) 0x465af4 STR	X2, [X1, X17,LSL #3]

    (2101) 0x465af8 ADD	X17, X17, #1

    (2101) 0x465afc LDR	X0, [X15, X10,LSL #3]

    (2101) 0x465b00 B	465ae0

0x465b04 LDP	X20, X19, [SP, #256]

0x465b08 LDP	X22, X21, [SP, #240]

0x465b0c LDP	X24, X23, [SP, #224]

0x465b10 LDP	X26, X25, [SP, #208]

0x465b14 LDP	X28, X27, [SP, #192]

0x465b18 LDP	X29, X30, [SP, #176]

0x465b1c ADD	SP, SP, #272

0x465b20 RET

0x465b24 HINT	#0

0x465b28 HINT	#0

0x465b2c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_5

Source file and lines	par_strength.c:246-513
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:246-283,289-302,309-386,392-415,422-445,451-472,480,492-513.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.83 to 0.67 cycles (37.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 60% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 24.83 to 19.50 cycles (1.27x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.83 to 1.00 cycles (24.83x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 520 bytes. The binary function is storing 240 bytes.

General properties

nb instructions	135
loop length	540
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	4.00	4.00	4.00	4.00	4.00	4.00	0.50	0.50	0.50	0.50	24.83	24.50	24.67	11.50	11.50
cycles	3.50	3.50	4.00	4.00	4.00	4.00	4.00	4.00	0.50	0.50	0.50	0.50	24.83	24.50	24.67	11.50	11.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.13
Overall L1	24.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.83 cycles. At this rate:

21% of peak load performance is reached (20.94 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.66 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 464ec0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X2, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X1, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X24, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X25, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X5, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a8a30 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X12, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X19, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X12, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4659d8 <hypre_BoomerAMGCreateS.omp_outlined.2+0xb18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X3, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X5, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D2, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D3, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVN X26, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X14, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X16, X15, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X18, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X2, X1, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X17, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X30, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STUR X3, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X5, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X5, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR D0, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X11, X0, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X19, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X11, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X3, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X24, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X7, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X19, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X7, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X19, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 464ffc <hypre_BoomerAMGCreateS.omp_outlined.2+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X9, X11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDUR X19, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X2, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X1, X8, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, X10, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a95f0 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X10, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X10, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 465b04 <hypre_BoomerAMGCreateS.omp_outlined.2+0xc44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X15, X13, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X14, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X12, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 465a4c <hypre_BoomerAMGCreateS.omp_outlined.2+0xb8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_5

Source file and lines	par_strength.c:246-513
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.83 to 1.00 cycles (24.83x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 520 bytes. The binary function is storing 240 bytes.

General properties

nb instructions	135
loop length	540
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	4.00	4.00	4.00	4.00	4.00	4.00	0.50	0.50	0.50	0.50	24.83	24.50	24.67	11.50	11.50
cycles	3.50	3.50	4.00	4.00	4.00	4.00	4.00	4.00	0.50	0.50	0.50	0.50	24.83	24.50	24.67	11.50	11.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.13
Overall L1	24.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.83 cycles. At this rate:

21% of peak load performance is reached (20.94 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.66 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 464ec0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X2, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X1, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X24, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X25, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X5, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a8a30 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X12, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X19, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X12, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4659d8 <hypre_BoomerAMGCreateS.omp_outlined.2+0xb18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X3, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X5, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D2, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D3, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVN X26, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X14, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X16, X15, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X18, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X2, X1, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X17, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X30, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STUR X3, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X5, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X5, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR D0, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X11, X0, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X19, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X11, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X3, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X24, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X7, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X19, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X7, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X19, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 464ffc <hypre_BoomerAMGCreateS.omp_outlined.2+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X9, X11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDUR X19, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X2, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X1, X8, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, X10, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a95f0 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X10, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X10, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 465b04 <hypre_BoomerAMGCreateS.omp_outlined.2+0xc44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X15, X13, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X14, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X12, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 465a4c <hypre_BoomerAMGCreateS.omp_outlined.2+0xb8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreateS.omp_outlined.2–	0.29	0.06
▼Loop 2100 - par_strength.c:492-513 - exec–	0.10	0.02
▼Loop 2099 - par_strength.c:492-513 - exec–	0.01	0.01
○Loop 2101 - par_strength.c:508-513 - exec	0.00	0.00
▼Loop 2107 - par_strength.c:253-472 - exec–	0.00	0.00
▼Loop 2108 - par_strength.c:253-472 - exec–	0.00	0.00
▼Loop 2102 - par_strength.c:253-472 - exec–	0.05	0.01
○Loop 2106 - par_strength.c:451-460 - exec	0.09	0.01
○Loop 2117 - par_strength.c:326-327 - exec	0.03	0.01
○Loop 2116 - par_strength.c:324-327 - exec	0.01	0.01
○Loop 2105 - par_strength.c:463-472 - exec	0.00	0.00
○Loop 2112 - par_strength.c:376-386 - exec	0.00	0.00
○Loop 2119 - par_strength.c:316-319 - exec	0.00	0.00
○Loop 2123 - par_strength.c:289-294 - exec	0.00	0.00
○Loop 2122 - par_strength.c:297-302 - exec	0.00	0.00
○Loop 2124 - par_strength.c:278-283 - exec	0.00	0.00
○Loop 2113 - par_strength.c:363-373 - exec	0.00	0.00
○Loop 2115 - par_strength.c:329-332 - exec	0.00	0.00
○Loop 2114 - par_strength.c:331-332 - exec	0.00	0.00
○Loop 2103 - par_strength.c:351-353 - exec	0.00	0.00
○Loop 2109 - par_strength.c:424-433 - exec	0.00	0.00
○Loop 2121 - par_strength.c:313-314 - exec	0.00	0.00
○Loop 2118 - par_strength.c:318-319 - exec	0.00	0.00
○Loop 2110 - par_strength.c:405-415 - exec	0.00	0.00
○Loop 2111 - par_strength.c:392-402 - exec	0.00	0.00
○Loop 2125 - par_strength.c:270-275 - exec	0.00	0.00
○Loop 2120 - par_strength.c:311-314 - exec	0.00	0.00
○Loop 2104 - par_strength.c:345-347 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code