OV - exec - Function hypre_ParMatmul._omp

	Function: hypre_ParMatmul._omp_fn.3	Module: exec	Source: par_csr_matop.c:829-995 [...]	Coverage (incl. loops): 1.15% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 829 - 995

--------------------------------------------------------------------------------

829: #pragma omp parallel

830: #endif

831:    {

832:     HYPRE_Int *B_marker = NULL;

[...]

840:     ii = hypre_GetThreadNum();

841:     num_threads = hypre_NumActiveThreads();

842:     size = num_rows_diag_A/num_threads;

843:     rest = num_rows_diag_A - size*num_threads;

844:     if (ii < rest)

845:     {

846:        ns = ii*size+ii;

847:        ne = (ii+1)*size+ii+1;

848:     }

849:     else

850:     {

851:        ns = ii*size+rest;

852:        ne = (ii+1)*size+rest;

853:     }

854:     jj_count_diag = C_diag_i[ns];

855:     jj_count_offd = C_offd_i[ns];

856:     if (num_cols_diag_B || num_cols_offd_C)

857:     B_marker = hypre_CTAlloc(HYPRE_Int, num_cols_diag_B+num_cols_offd_C);

858:     for (i1 = 0; i1 < num_cols_diag_B+num_cols_offd_C; i1++)

859:       B_marker[i1] = -1;

[...]

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

879:          jj_count_diag++;

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

[...]

995:     hypre_TFree(B_marker);

0x5002c0 STP	X29, X30, [SP, #704]!

0x5002c4 ADD	X29, SP, #0

0x5002c8 ORR	X2, XZR, X0

0x5002cc STP	X19, X20, [SP, #16]

0x5002d0 STP	X21, X22, [SP, #32]

0x5002d4 STP	X23, X24, [SP, #48]

0x5002d8 STP	X25, X26, [SP, #64]

0x5002dc STP	X27, X28, [SP, #80]

0x5002e0 STR	D15, [SP, #96]

0x5002e4 LDP	X0, X1, [X0]

0x5002e8 STR	X1, [SP, #120]

0x5002ec STR	X0, [SP, #192]

0x5002f0 LDP	X15, X3, [X2, #16]

0x5002f4 STR	X15, [SP, #224]

0x5002f8 STR	X3, [SP, #288]

0x5002fc LDP	X4, X5, [X2, #32]

0x500300 STR	X4, [SP, #112]

0x500304 STR	X5, [SP, #280]

0x500308 LDP	X25, X14, [X2, #48]

0x50030c STR	X14, [SP, #216]

0x500310 LDP	X21, X7, [X2, #80]

0x500314 LDP	X22, X27, [X2, #64]

0x500318 STR	X7, [SP, #208]

0x50031c LDP	X8, X6, [X2, #96]

0x500320 STR	X6, [SP, #200]

0x500324 STR	X8, [SP, #184]

0x500328 LDP	X26, X9, [X2, #112]

0x50032c LDR	X10, [X2, #176]

0x500330 STR	X9, [SP, #176]

0x500334 LDP	X11, X19, [X2, #128]

0x500338 LDR	D15, [X2, #248]

0x50033c STR	X11, [SP, #168]

0x500340 LDP	X24, X23, [X2, #152]

0x500344 STR	X10, [SP, #160]

0x500348 LDP	X12, X13, [X2, #192]

0x50034c STR	X12, [SP, #144]

0x500350 STR	X13, [SP, #272]

0x500354 LDP	X28, X18, [X2, #208]

0x500358 STR	X18, [SP, #136]

0x50035c LDP	X16, X17, [X2, #224]

0x500360 STR	X2, [SP, #128]

0x500364 STP	X17, X16, [SP, #256]

0x500368 LDR	X20, [X2, #240]

0x50036c STR	X20, [SP, #152]

0x500370 BL	5499c0

0x500374 ORR	X20, XZR, X0

0x500378 BL	5499a0

0x50037c ORR	X2, XZR, X0

0x500380 SDIV	X0, X25, X0

0x500384 LDR	X3, [SP, #144]

0x500388 LDP	X12, X18, [SP, #128]

0x50038c LDP	X4, X5, [SP, #160]

0x500390 LDP	X6, X7, [SP, #200]

0x500394 MSUB	X25, X0, X2, X25

0x500398 LDP	X14, X15, [SP, #216]

0x50039c MADD	X1, X20, X0, XZR

0x5003a0 CMP	X20, X25

0x5003a4 ADD	X9, X0, X1

0x5003a8 B.GE	5007e4

0x5003ac ADD	X30, X20, X9

0x5003b0 ADD	X8, X20, X1

0x5003b4 ADD	X13, X30, #1

0x5003b8 LDR	X11, [X12, #184]

0x5003bc UBFM	X9, X8, #61, #60

0x5003c0 LDR	X10, [X12, #144]

0x5003c4 LDR	X16, [X12, #168]

0x5003c8 LDR	X17, [X11]

0x5003cc LDR	X20, [X10]

0x5003d0 LDR	X2, [X16]

0x5003d4 ORR	X0, X26, X17

0x5003d8 LDR	X20, [X20, X9]

0x5003dc LDR	X25, [X2, X9]

0x5003e0 CBNZ	X0, 500768

0x5003e4 MOVZ	X0, #0

0x5003e8 LDR	X1, [SP, #112]

0x5003ec LDR	X17, [SP, #120]

0x5003f0 ADD	X12, X1, X9

0x5003f4 ADD	X10, X17, X9

0x5003f8 CMP	X8, X13

0x5003fc B.GE	500748

0x500400 STR	X4, [SP, #112]

0x500404 ORR	X16, XZR, X15

0x500408 STP	X23, X12, [SP, #136]

0x50040c LDR	X23, [SP, #152]

0x500410 STP	X13, X14, [SP, #160]

0x500414 STR	X5, [SP, #200]

0x500418 STP	X18, X28, [SP, #296]

0x50041c STR	X3, [SP, #312]

0x500420 CBNZ	X23, 5004f4

  (3131) 0x500424 LDR	X18, [SP, #168]

  (3131) 0x500428 ORR	X2, XZR, X20

  (3131) 0x50042c ORR	X9, XZR, X25

  (3131) 0x500430 CBNZ	X18, 500514

  (3131) 0x500434 LDP	X12, X4, [X10]

  (3131) 0x500438 CMP	X12, X4

  (3131) 0x50043c B.GE	5004c4

  (3131) 0x500440 LDP	X17, X18, [SP, #176]

  (3131) 0x500444 LDP	X13, X11, [SP, #192]

  (3131) 0x500448 STR	X8, [SP, #120]

    (3136) 0x50044c LDR	X23, [X16, X12,LSL #3]

    (3136) 0x500450 LDR	D28, [X13, X12,LSL #3]

    (3136) 0x500454 UBFM	X5, X23, #61, #60

    (3136) 0x500458 ADD	X8, X5, #8

    (3136) 0x50045c LDR	X1, [X27, X5]

    (3136) 0x500460 ADD	X15, X27, X8

    (3136) 0x500464 LDR	X14, [X27, X8]

    (3136) 0x500468 CMP	X1, X14

    (3136) 0x50046c B.GE	5004ac

      (3138) 0x500470 LDR	X4, [X21, X1,LSL #3]

      (3138) 0x500474 UBFM	X28, X2, #61, #60

      (3138) 0x500478 LDR	D6, [X22, X1,LSL #3]

      (3138) 0x50047c UBFM	X23, X4, #61, #60

      (3138) 0x500480 LDR	X3, [X0, X23]

      (3138) 0x500484 FMUL	D7, D28, D6

      (3138) 0x500488 UBFM	X30, X3, #61, #60

      (3138) 0x50048c CMP	X20, X3

      (3138) 0x500490 B.GT	500644

      (3138) 0x500494 LDR	D16, [X19, X30]

      (3138) 0x500498 ADD	X1, X1, #1

      (3138) 0x50049c FADD	D17, D16, D7

      (3138) 0x5004a0 STR	D17, [X19, X30]

      (3138) 0x5004a4 CMP	X1, X14

      (3138) 0x5004a8 B.LT	500470

    (3136) 0x5004ac CBNZ	X17, 500668

    (3136) 0x5004b0 LDR	X4, [X10, #8]

    (3136) 0x5004b4 ADD	X12, X12, #1

    (3136) 0x5004b8 CMP	X4, X12

    (3136) 0x5004bc B.GT	50044c

  (3131) 0x5004c0 LDR	X8, [SP, #120]

  (3131) 0x5004c4 ADD	X8, X8, #1

  (3131) 0x5004c8 ADD	X10, X10, #8

  (3131) 0x5004cc LDR	X20, [SP, #144]

  (3131) 0x5004d0 LDR	X17, [SP, #160]

  (3131) 0x5004d4 ADD	X25, X20, #8

  (3131) 0x5004d8 STR	X25, [SP, #144]

  (3131) 0x5004dc CMP	X17, X8

  (3131) 0x5004e0 B.EQ	500748

  (3131) 0x5004e4 LDR	X23, [SP, #152]

  (3131) 0x5004e8 ORR	X25, XZR, X9

  (3131) 0x5004ec ORR	X20, XZR, X2

  (3131) 0x5004f0 CBZ	X23, 500424

(3135) 0x5004f4 UBFM	X28, X20, #61, #60

(3135) 0x5004f8 STR	X20, [X0, X8,LSL #3]

(3135) 0x5004fc ADD	X2, X20, #1

(3135) 0x500500 LDR	X18, [SP, #168]

(3135) 0x500504 ORR	X9, XZR, X25

(3135) 0x500508 STR	D15, [X19, X28]

(3135) 0x50050c STR	X8, [X24, X28]

(3135) 0x500510 CBZ	X18, 500434

  (3131) 0x500514 LDR	X5, [SP, #144]

  (3131) 0x500518 LDP	X13, X3, [X5]

  (3131) 0x50051c CMP	X13, X3

  (3131) 0x500520 B.GE	500434

  (3131) 0x500524 LDR	X4, [SP, #112]

  (3131) 0x500528 LDP	X14, X15, [SP, #272]

  (3131) 0x50052c LDP	X18, X28, [SP, #296]

  (3131) 0x500530 STP	X22, X16, [SP, #240]

  (3131) 0x500534 ORR	X22, XZR, X10

  (3131) 0x500538 LDR	X23, [SP, #136]

  (3131) 0x50053c STP	X21, X27, [SP, #224]

  (3131) 0x500540 ORR	X21, XZR, X5

  (3131) 0x500544 ORR	X27, XZR, X8

  (3131) 0x500548 LDR	X17, [SP, #256]

  (3131) 0x50054c STP	X6, X7, [SP, #208]

  (3131) 0x500550 LDR	X10, [SP, #264]

  (3131) 0x500554 LDR	X16, [SP, #288]

  (3131) 0x500558 LDR	X3, [SP, #312]

  (3131) 0x50055c HINT	#0

    (3132) 0x500560 LDR	X6, [X15, X13,LSL #3]

    (3132) 0x500564 LDR	D31, [X16, X13,LSL #3]

    (3132) 0x500568 UBFM	X7, X6, #61, #60

    (3132) 0x50056c ADD	X8, X7, #8

    (3132) 0x500570 LDR	X1, [X10, X7]

    (3132) 0x500574 ADD	X12, X10, X8

    (3132) 0x500578 LDR	X11, [X10, X8]

    (3132) 0x50057c CMP	X1, X11

    (3132) 0x500580 B.GE	5005cc

    (3132) 0x500584 STP	X10, X28, [SP, #120]

      (3134) 0x500588 UBFM	X28, X9, #61, #60

      (3134) 0x50058c LDR	X10, [X17, X1,LSL #3]

      (3134) 0x500590 LDR	D1, [X18, X1,LSL #3]

      (3134) 0x500594 ADD	X30, X26, X10

      (3134) 0x500598 UBFM	X5, X30, #61, #60

      (3134) 0x50059c LDR	X6, [X0, X5]

      (3134) 0x5005a0 FMUL	D2, D31, D1

      (3134) 0x5005a4 UBFM	X30, X6, #61, #60

      (3134) 0x5005a8 CMP	X25, X6

      (3134) 0x5005ac B.GT	500724

      (3134) 0x5005b0 LDR	D0, [X23, X30]

      (3134) 0x5005b4 ADD	X1, X1, #1

      (3134) 0x5005b8 FADD	D3, D0, D2

      (3134) 0x5005bc STR	D3, [X23, X30]

      (3134) 0x5005c0 CMP	X1, X11

      (3134) 0x5005c4 B.LT	500588

    (3132) 0x5005c8 LDP	X10, X28, [SP, #120]

    (3132) 0x5005cc ADD	X12, X14, X8

    (3132) 0x5005d0 LDR	X1, [X14, X7]

    (3132) 0x5005d4 LDR	X30, [X14, X8]

    (3132) 0x5005d8 CMP	X1, X30

    (3132) 0x5005dc B.GE	50061c

      (3133) 0x5005e0 LDR	X6, [X28, X1,LSL #3]

      (3133) 0x5005e4 UBFM	X8, X2, #61, #60

      (3133) 0x5005e8 LDR	D30, [X3, X1,LSL #3]

      (3133) 0x5005ec UBFM	X7, X6, #61, #60

      (3133) 0x5005f0 LDR	X5, [X0, X7]

      (3133) 0x5005f4 FMUL	D4, D31, D30

      (3133) 0x5005f8 UBFM	X11, X5, #61, #60

      (3133) 0x5005fc CMP	X20, X5

      (3133) 0x500600 B.GT	5006f0

      (3133) 0x500604 LDR	D29, [X19, X11]

      (3133) 0x500608 ADD	X1, X1, #1

      (3133) 0x50060c FADD	D5, D29, D4

      (3133) 0x500610 STR	D5, [X19, X11]

      (3133) 0x500614 CMP	X1, X30

      (3133) 0x500618 B.LT	5005e0

    (3132) 0x50061c LDR	X12, [X21, #8]

    (3132) 0x500620 ADD	X13, X13, #1

    (3132) 0x500624 CMP	X12, X13

    (3132) 0x500628 B.GT	500560

  (3131) 0x50062c ORR	X8, XZR, X27

  (3131) 0x500630 ORR	X10, XZR, X22

  (3131) 0x500634 LDP	X6, X7, [SP, #208]

  (3131) 0x500638 LDP	X21, X27, [SP, #224]

  (3131) 0x50063c LDP	X22, X16, [SP, #240]

  (3131) 0x500640 B	500434

      (3138) 0x500644 STR	X2, [X0, X23]

      (3138) 0x500648 ADD	X1, X1, #1

      (3138) 0x50064c ADD	X2, X2, #1

      (3138) 0x500650 STR	D7, [X19, X28]

      (3138) 0x500654 STR	X4, [X24, X28]

      (3138) 0x500658 LDR	X14, [X15]

      (3138) 0x50065c CMP	X14, X1

      (3138) 0x500660 B.GT	500470

    (3136) 0x500664 CBZ	X17, 5004b0

    (3136) 0x500668 LDR	X1, [X18, X5]

    (3136) 0x50066c ADD	X4, X18, X8

    (3136) 0x500670 LDR	X30, [X18, X8]

    (3136) 0x500674 CMP	X1, X30

    (3136) 0x500678 B.GE	5004b0

    (3136) 0x50067c LDR	X28, [SP, #136]

      (3137) 0x500680 UBFM	X23, X9, #61, #60

      (3137) 0x500684 LDR	X5, [X6, X1,LSL #3]

      (3137) 0x500688 LDR	D27, [X7, X1,LSL #3]

      (3137) 0x50068c LDR	X8, [X11, X5,LSL #3]

      (3137) 0x500690 FMUL	D18, D28, D27

      (3137) 0x500694 ADD	X15, X26, X8

      (3137) 0x500698 UBFM	X3, X15, #61, #60

      (3137) 0x50069c LDR	X14, [X0, X3]

      (3137) 0x5006a0 UBFM	X5, X14, #61, #60

      (3137) 0x5006a4 CMP	X25, X14

      (3137) 0x5006a8 B.GT	5006c8

      (3137) 0x5006ac LDR	D26, [X28, X5]

      (3137) 0x5006b0 ADD	X1, X1, #1

      (3137) 0x5006b4 FADD	D19, D26, D18

      (3137) 0x5006b8 STR	D19, [X28, X5]

      (3137) 0x5006bc CMP	X1, X30

      (3137) 0x5006c0 B.LT	500680

    (3136) 0x5006c4 B	5004b0

      (3137) 0x5006c8 LDR	X30, [SP, #112]

      (3137) 0x5006cc ADD	X1, X1, #1

      (3137) 0x5006d0 STR	X9, [X0, X3]

      (3137) 0x5006d4 ADD	X9, X9, #1

      (3137) 0x5006d8 STR	D18, [X28, X23]

      (3137) 0x5006dc STR	X8, [X30, X23]

      (3137) 0x5006e0 LDR	X30, [X4]

      (3137) 0x5006e4 CMP	X30, X1

      (3137) 0x5006e8 B.GT	500680

    (3136) 0x5006ec B	5004b0

      (3133) 0x5006f0 STR	X2, [X0, X7]

      (3133) 0x5006f4 ADD	X1, X1, #1

      (3133) 0x5006f8 ADD	X2, X2, #1

      (3133) 0x5006fc STR	D4, [X19, X8]

      (3133) 0x500700 STR	X6, [X24, X8]

      (3133) 0x500704 LDR	X30, [X12]

      (3133) 0x500708 CMP	X30, X1

      (3133) 0x50070c B.GT	5005e0

    (3132) 0x500710 LDR	X12, [X21, #8]

    (3132) 0x500714 ADD	X13, X13, #1

    (3132) 0x500718 CMP	X12, X13

    (3132) 0x50071c B.GT	500560

  (3131) 0x500720 B	50062c

      (3134) 0x500724 STR	X9, [X0, X5]

      (3134) 0x500728 ADD	X1, X1, #1

      (3134) 0x50072c ADD	X9, X9, #1

      (3134) 0x500730 STR	D2, [X23, X28]

      (3134) 0x500734 STR	X10, [X4, X28]

      (3134) 0x500738 LDR	X11, [X12]

      (3134) 0x50073c CMP	X11, X1

      (3134) 0x500740 B.GT	500588

    (3132) 0x500744 B	5005c8

0x500748 LDR	D15, [SP, #96]

0x50074c LDP	X19, X20, [SP, #16]

0x500750 LDP	X21, X22, [SP, #32]

0x500754 LDP	X23, X24, [SP, #48]

0x500758 LDP	X25, X26, [SP, #64]

0x50075c LDP	X27, X28, [SP, #80]

0x500760 LDP	X29, X30, [SP], #320

0x500764 B	546e20

0x500768 MOVZ	X1, #8

0x50076c ADD	X0, X26, X17

0x500770 STP	X13, X18, [SP, #128]

0x500774 STR	X3, [SP, #144]

0x500778 STP	X4, X5, [SP, #160]

0x50077c STP	X6, X7, [SP, #200]

0x500780 STP	X14, X15, [SP, #216]

0x500784 STP	X9, X8, [SP, #232]

0x500788 STR	X12, [SP, #248]

0x50078c BL	546d88

0x500790 LDR	X10, [SP, #248]

0x500794 MOVZ	X1, #0

0x500798 MOVN	X12, #0

0x50079c LDP	X13, X18, [SP, #128]

0x5007a0 LDP	X4, X5, [SP, #160]

0x5007a4 LDP	X6, X7, [SP, #200]

0x5007a8 LDP	X14, X15, [SP, #216]

0x5007ac LDP	X9, X8, [SP, #232]

0x5007b0 LDR	X11, [X10, #184]

0x5007b4 LDR	X3, [SP, #144]

0x5007b8 LDR	X2, [X11]

0x5007bc ADD	X10, X26, X2

0x5007c0 CMP	X10, #0

0x5007c4 B.LE	5003e8

(3139) 0x5007c8 STR	X12, [X0, X1,LSL #3]

(3139) 0x5007cc ADD	X1, X1, #1

(3139) 0x5007d0 LDR	X30, [X11]

(3139) 0x5007d4 ADD	X16, X26, X30

(3139) 0x5007d8 CMP	X16, X1

(3139) 0x5007dc B.GT	5007c8

0x5007e0 B	5003e8

0x5007e4 ADD	X8, X25, X1

0x5007e8 ADD	X13, X25, X9

0x5007ec B	5003b8

Coverage (%)	Name	Source Location	Module
►99.08+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	par_csr_matop.c:829-995
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:829-832,840-859,865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989,995.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 29.17 to 3.50 cycles (8.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 71% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 29.17 to 23.67 cycles (1.23x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 29.17 to 1.50 cycles (19.44x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 608 bytes. The binary function is storing 432 bytes.

General properties

nb instructions	125
loop length	500
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	5.50	5.50	5.17	5.17	5.17	5.17	5.17	5.17	0.50	0.50	0.00	0.00	29.17	28.83	29.00	19.00	19.00
cycles	5.50	5.50	5.17	5.17	5.17	5.17	5.17	5.17	0.50	0.50	0.00	0.00	29.17	28.83	29.00	19.00	19.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	15.63
Overall L1	29.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.17 cycles. At this rate:

21% of peak load performance is reached (20.85 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.81 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 5002c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #704]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X2, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDP X0, X1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X3, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X4, X5, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X25, X14, [X2, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X14, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X7, [X2, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X27, [X2, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X7, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X6, [X2, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X6, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X26, X9, [X2, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X10, [X2, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X11, X19, [X2, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR D15, [X2, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR X11, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X24, X23, [X2, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X10, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X12, X13, [X2, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X28, X18, [X2, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X16, X17, [X2, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X17, X16, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X20, [X2, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 5499c0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
BL 5499a0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X0, X25, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
LDR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X12, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X4, X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X6, X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB X25, X0, X2, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDP X14, X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MADD X1, X20, X0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X20, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X9, X0, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B.GE 5007e4 <hypre_ParMatmul._omp_fn.3+0x524>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X20, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X8, X20, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X30, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [X12, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X9, X8, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X12, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X20, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, X26, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X20, [X20, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X2, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 500768 <hypre_ParMatmul._omp_fn.3+0x4a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X17, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X12, X1, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X17, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 500748 <hypre_ParMatmul._omp_fn.3+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X16, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STP X23, X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X23, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X13, X14, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X5, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X28, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X3, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBNZ X23, 5004f4 <hypre_ParMatmul._omp_fn.3+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #320	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 546e20 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X26, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STP X13, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X4, X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X14, X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X9, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X12, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 546d88 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVN X12, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP X13, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X4, X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X6, X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X14, X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X9, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X11, [X10, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X26, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 5003e8 <hypre_ParMatmul._omp_fn.3+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 5003e8 <hypre_ParMatmul._omp_fn.3+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X25, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X25, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B 5003b8 <hypre_ParMatmul._omp_fn.3+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_2

Source file and lines	par_csr_matop.c:829-995
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 29.17 to 3.50 cycles (8.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 29.17 to 1.50 cycles (19.44x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 608 bytes. The binary function is storing 432 bytes.

General properties

nb instructions	125
loop length	500
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	5.50	5.50	5.17	5.17	5.17	5.17	5.17	5.17	0.50	0.50	0.00	0.00	29.17	28.83	29.00	19.00	19.00
cycles	5.50	5.50	5.17	5.17	5.17	5.17	5.17	5.17	0.50	0.50	0.00	0.00	29.17	28.83	29.00	19.00	19.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	15.63
Overall L1	29.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.17 cycles. At this rate:

21% of peak load performance is reached (20.85 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.81 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 5002c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #704]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X2, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDP X0, X1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X3, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X4, X5, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X25, X14, [X2, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X14, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X7, [X2, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X27, [X2, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X7, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X6, [X2, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X6, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X26, X9, [X2, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X10, [X2, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X11, X19, [X2, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR D15, [X2, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR X11, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X24, X23, [X2, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X10, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X12, X13, [X2, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X28, X18, [X2, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X16, X17, [X2, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X17, X16, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X20, [X2, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 5499c0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
BL 5499a0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X0, X25, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
LDR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X12, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X4, X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X6, X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB X25, X0, X2, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDP X14, X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MADD X1, X20, X0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X20, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X9, X0, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B.GE 5007e4 <hypre_ParMatmul._omp_fn.3+0x524>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X20, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X8, X20, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X30, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [X12, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X9, X8, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X12, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X20, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, X26, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X20, [X20, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X2, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 500768 <hypre_ParMatmul._omp_fn.3+0x4a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X17, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X12, X1, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X17, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 500748 <hypre_ParMatmul._omp_fn.3+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X16, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STP X23, X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X23, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X13, X14, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X5, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X28, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X3, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBNZ X23, 5004f4 <hypre_ParMatmul._omp_fn.3+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #320	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 546e20 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X26, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STP X13, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X4, X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X14, X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X9, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X12, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 546d88 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVN X12, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP X13, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X4, X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X6, X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X14, X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X9, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X11, [X10, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X26, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 5003e8 <hypre_ParMatmul._omp_fn.3+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 5003e8 <hypre_ParMatmul._omp_fn.3+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X25, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X25, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B 5003b8 <hypre_ParMatmul._omp_fn.3+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_ParMatmul._omp_fn.3–	1.15	0.18
○Loop 3139 - par_csr_matop.c:858-859 - exec	0.00	0.00
▼Loop 3135 - par_csr_matop.c:865-989 - exec–	0.00	0.00
▼Loop 3131 - par_csr_matop.c:865-989 - exec–	0.02	0.01
▼Loop 3136 - par_csr_matop.c:937-989 - exec–	0.26	0.03
○Loop 3138 - par_csr_matop.c:946-965 - exec	0.86	0.11
○Loop 3137 - par_csr_matop.c:970-989 - exec	0.00	0.00
▼Loop 3132 - par_csr_matop.c:888-928 - exec–	0.00	0.00
○Loop 3133 - par_csr_matop.c:917-928 - exec	0.00	0.00
○Loop 3134 - par_csr_matop.c:897-915 - exec	0.00	0.00

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code