OV - FFTW CLANG - Function t1fv

	Function: t1fv_8#0x1b6dd0	Module: bench	Source: t1fv_8.c:141-202 [...]	Coverage (incl. loops): 25.82% \| (excl. loops): 0.01%

/home/fmusial/FFTW_Benchmarks/fftw-3.3.10-clang/dft/simd/avx2/../../../simd-support/simd-avx2.h: 85 - 315

--------------------------------------------------------------------------------

85:      SUFF(_mm256_storeu_p)(x, v);

[...]

252:      return VPERM1(x, DS(SHUFVALD(1, 0), SHUFVALS(1, 0, 3, 2)));

[...]

280:      return VXOR(pmpm.v, x);

[...]

315:      return SUFF(_mm256_fmsubadd_p)(sr, VDUPL(tx), VMUL(FLIP_RI(sr), VDUPH(tx)));

/home/fmusial/FFTW_Benchmarks/fftw-3.3.10-clang/dft/simd/avx2/./../common/t1fv_8.c: 141 - 202

--------------------------------------------------------------------------------

141: 	  for (m = mb, W = W + (mb * ((TWVL / VL) * 14)); m < me; m = m + VL, x = x + (VL * ms), W = W + (TWVL * 14), MAKE_VOLATILE_STRIDE(8, rs)) {

142: 	       V T4, Tq, Tm, Tr, T9, Tt, Te, Tu, T1, T3, T2;

143: 	       T1 = LD(&(x[0]), ms, &(x[0]));

144: 	       T2 = LD(&(x[WS(rs, 4)]), ms, &(x[0]));

145: 	       T3 = BYTWJ(&(W[TWVL * 6]), T2);

146: 	       T4 = VSUB(T1, T3);

147: 	       Tq = VADD(T1, T3);

148: 	       {

149: 		    V Tj, Tl, Ti, Tk;

150: 		    Ti = LD(&(x[WS(rs, 2)]), ms, &(x[0]));

151: 		    Tj = BYTWJ(&(W[TWVL * 2]), Ti);

152: 		    Tk = LD(&(x[WS(rs, 6)]), ms, &(x[0]));

153: 		    Tl = BYTWJ(&(W[TWVL * 10]), Tk);

154: 		    Tm = VSUB(Tj, Tl);

155: 		    Tr = VADD(Tj, Tl);

156: 	       }

157: 	       {

158: 		    V T6, T8, T5, T7;

159: 		    T5 = LD(&(x[WS(rs, 1)]), ms, &(x[WS(rs, 1)]));

160: 		    T6 = BYTWJ(&(W[0]), T5);

161: 		    T7 = LD(&(x[WS(rs, 5)]), ms, &(x[WS(rs, 1)]));

162: 		    T8 = BYTWJ(&(W[TWVL * 8]), T7);

163: 		    T9 = VSUB(T6, T8);

164: 		    Tt = VADD(T6, T8);

165: 	       }

166: 	       {

167: 		    V Tb, Td, Ta, Tc;

168: 		    Ta = LD(&(x[WS(rs, 7)]), ms, &(x[WS(rs, 1)]));

169: 		    Tb = BYTWJ(&(W[TWVL * 12]), Ta);

170: 		    Tc = LD(&(x[WS(rs, 3)]), ms, &(x[WS(rs, 1)]));

171: 		    Td = BYTWJ(&(W[TWVL * 4]), Tc);

172: 		    Te = VSUB(Tb, Td);

173: 		    Tu = VADD(Tb, Td);

174: 	       }

175: 	       {

176: 		    V Ts, Tv, Tw, Tx;

177: 		    Ts = VADD(Tq, Tr);

178: 		    Tv = VADD(Tt, Tu);

179: 		    ST(&(x[WS(rs, 4)]), VSUB(Ts, Tv), ms, &(x[0]));

180: 		    ST(&(x[0]), VADD(Ts, Tv), ms, &(x[0]));

181: 		    Tw = VSUB(Tq, Tr);

182: 		    Tx = VBYI(VSUB(Tu, Tt));

183: 		    ST(&(x[WS(rs, 6)]), VSUB(Tw, Tx), ms, &(x[0]));

184: 		    ST(&(x[WS(rs, 2)]), VADD(Tw, Tx), ms, &(x[0]));

185: 		    {

186: 			 V Tg, To, Tn, Tp, Tf, Th;

187: 			 Tf = VMUL(LDK(KP707106781), VADD(T9, Te));

188: 			 Tg = VADD(T4, Tf);

189: 			 To = VSUB(T4, Tf);

190: 			 Th = VMUL(LDK(KP707106781), VSUB(Te, T9));

191: 			 Tn = VBYI(VSUB(Th, Tm));

192: 			 Tp = VBYI(VADD(Tm, Th));

193: 			 ST(&(x[WS(rs, 7)]), VSUB(Tg, Tn), ms, &(x[WS(rs, 1)]));

194: 			 ST(&(x[WS(rs, 3)]), VADD(To, Tp), ms, &(x[WS(rs, 1)]));

195: 			 ST(&(x[WS(rs, 1)]), VADD(Tg, Tn), ms, &(x[WS(rs, 1)]));

196: 			 ST(&(x[WS(rs, 5)]), VSUB(To, Tp), ms, &(x[WS(rs, 1)]));

197: 		    }

198: 	       }

199: 	  }

200:      }

201:      VLEAVE();

202: }

0x1b6dd0 CMP	%R9,%R8

0x1b6dd3 JGE	1b702b

0x1b6dd9 PUSH	%RBP

0x1b6dda MOV	%RSP,%RBP

0x1b6ddd PUSH	%RBX

0x1b6dde MOV	0x10(%RBP),%RAX

0x1b6de2 IMUL	$0x70,%R8,%R10

0x1b6de6 SAL	$0x4,%RAX

0x1b6dea LEA	0x12ff77(%RIP),%RSI

0x1b6df1 MOV	(%RSI),%RSI

0x1b6df4 ADD	%R10,%RDX

0x1b6df7 ADD	$0xc0,%RDX

0x1b6dfe ADD	$0x38,%RCX

0x1b6e02 SAL	$0x3,%RSI

0x1b6e06 VBROADCASTI128	0x115071(%RIP),%YMM0

0x1b6e0f VBROADCASTSD	0x1140b0(%RIP),%YMM1

0x1b6e18 NOPL	(%RAX,%RAX,1)

(1310) 0x1b6e20 VMOVUPD	(%RDI),%YMM3

(1310) 0x1b6e24 MOV	-0x18(%RCX),%R10

(1310) 0x1b6e28 VMOVUPD	(%RDI,%R10,8),%YMM2

(1310) 0x1b6e2e VMOVUPD	-0xc0(%RDX),%YMM5

(1310) 0x1b6e36 VMOVUPD	-0xa0(%RDX),%YMM4

(1310) 0x1b6e3e VMOVUPD	-0x80(%RDX),%YMM6

(1310) 0x1b6e43 VMOVUPD	-0x60(%RDX),%YMM7

(1310) 0x1b6e48 VMOVDDUP	%YMM7,%YMM8

(1310) 0x1b6e4c VSHUFPD	$0x5,%YMM2,%YMM2,%YMM9

(1310) 0x1b6e51 VSHUFPD	$0xf,%YMM7,%YMM7,%YMM7

(1310) 0x1b6e56 VMULPD	%YMM7,%YMM9,%YMM7

(1310) 0x1b6e5a VFMSUBADD231PD	%YMM8,%YMM2,%YMM7

(1310) 0x1b6e5f VSUBPD	%YMM7,%YMM3,%YMM2

(1310) 0x1b6e63 VADDPD	%YMM7,%YMM3,%YMM3

(1310) 0x1b6e67 MOV	-0x30(%RCX),%R11

(1310) 0x1b6e6b MOV	-0x28(%RCX),%RBX

(1310) 0x1b6e6f VMOVUPD	(%RDI,%RBX,8),%YMM7

(1310) 0x1b6e74 VMOVDDUP	%YMM4,%YMM8

(1310) 0x1b6e78 VSHUFPD	$0x5,%YMM7,%YMM7,%YMM9

(1310) 0x1b6e7d VSHUFPD	$0xf,%YMM4,%YMM4,%YMM4

(1310) 0x1b6e82 VMULPD	%YMM4,%YMM9,%YMM9

(1310) 0x1b6e86 VFMSUBADD231PD	%YMM8,%YMM7,%YMM9

(1310) 0x1b6e8b MOV	-0x8(%RCX),%RBX

(1310) 0x1b6e8f VMOVUPD	(%RDI,%RBX,8),%YMM4

(1310) 0x1b6e94 VMOVUPD	-0x20(%RDX),%YMM7

(1310) 0x1b6e99 VMOVDDUP	%YMM7,%YMM8

(1310) 0x1b6e9d VSHUFPD	$0x5,%YMM4,%YMM4,%YMM10

(1310) 0x1b6ea2 VSHUFPD	$0xf,%YMM7,%YMM7,%YMM7

(1310) 0x1b6ea7 VMULPD	%YMM7,%YMM10,%YMM7

(1310) 0x1b6eab VFMSUBADD231PD	%YMM8,%YMM4,%YMM7

(1310) 0x1b6eb0 VSUBPD	%YMM7,%YMM9,%YMM4

(1310) 0x1b6eb4 VADDPD	%YMM7,%YMM9,%YMM7

(1310) 0x1b6eb8 VMOVUPD	(%RDI,%R11,8),%YMM8

(1310) 0x1b6ebe VMOVDDUP	%YMM5,%YMM9

(1310) 0x1b6ec2 VSHUFPD	$0x5,%YMM8,%YMM8,%YMM10

(1310) 0x1b6ec8 VSHUFPD	$0xf,%YMM5,%YMM5,%YMM5

(1310) 0x1b6ecd VMULPD	%YMM5,%YMM10,%YMM5

(1310) 0x1b6ed1 MOV	-0x10(%RCX),%R11

(1310) 0x1b6ed5 VMOVUPD	(%RDI,%R11,8),%YMM10

(1310) 0x1b6edb VFMSUBADD231PD	%YMM9,%YMM8,%YMM5

(1310) 0x1b6ee0 VMOVUPD	-0x40(%RDX),%YMM8

(1310) 0x1b6ee5 VMOVDDUP	%YMM8,%YMM9

(1310) 0x1b6eea VSHUFPD	$0x5,%YMM10,%YMM10,%YMM11

(1310) 0x1b6ef0 VSHUFPD	$0xf,%YMM8,%YMM8,%YMM8

(1310) 0x1b6ef6 VMULPD	%YMM11,%YMM8,%YMM8

(1310) 0x1b6efb VFMSUBADD231PD	%YMM9,%YMM10,%YMM8

(1310) 0x1b6f00 VSUBPD	%YMM8,%YMM5,%YMM9

(1310) 0x1b6f05 MOV	(%RCX),%R11

(1310) 0x1b6f08 VMOVUPD	(%RDI,%R11,8),%YMM10

(1310) 0x1b6f0e VADDPD	%YMM5,%YMM8,%YMM5

(1310) 0x1b6f12 VMOVUPD	(%RDX),%YMM8

(1310) 0x1b6f16 VMOVDDUP	%YMM8,%YMM11

(1310) 0x1b6f1b VSHUFPD	$0x5,%YMM10,%YMM10,%YMM12

(1310) 0x1b6f21 VSHUFPD	$0xf,%YMM8,%YMM8,%YMM8

(1310) 0x1b6f27 VMULPD	%YMM12,%YMM8,%YMM8

(1310) 0x1b6f2c VFMSUBADD231PD	%YMM11,%YMM10,%YMM8

(1310) 0x1b6f31 MOV	-0x20(%RCX),%R11

(1310) 0x1b6f35 VMOVUPD	(%RDI,%R11,8),%YMM10

(1310) 0x1b6f3b VMOVDDUP	%YMM6,%YMM11

(1310) 0x1b6f3f VSHUFPD	$0x5,%YMM10,%YMM10,%YMM12

(1310) 0x1b6f45 VSHUFPD	$0xf,%YMM6,%YMM6,%YMM6

(1310) 0x1b6f4a VMULPD	%YMM6,%YMM12,%YMM6

(1310) 0x1b6f4e VFMSUBADD231PD	%YMM11,%YMM10,%YMM6

(1310) 0x1b6f53 VSUBPD	%YMM6,%YMM8,%YMM10

(1310) 0x1b6f57 VADDPD	%YMM6,%YMM8,%YMM6

(1310) 0x1b6f5b VADDPD	%YMM7,%YMM3,%YMM8

(1310) 0x1b6f5f VADDPD	%YMM6,%YMM5,%YMM11

(1310) 0x1b6f63 VSUBPD	%YMM11,%YMM8,%YMM12

(1310) 0x1b6f68 VMOVUPD	%YMM12,(%RDI,%R10,8)

(1310) 0x1b6f6e VADDPD	%YMM11,%YMM8,%YMM8

(1310) 0x1b6f73 VMOVUPD	%YMM8,(%RDI)

(1310) 0x1b6f77 VSUBPD	%YMM7,%YMM3,%YMM3

(1310) 0x1b6f7b VSUBPD	%YMM5,%YMM6,%YMM5

(1310) 0x1b6f7f VXORPD	%YMM0,%YMM5,%YMM5

(1310) 0x1b6f83 VSHUFPS	$0x4e,%YMM5,%YMM5,%YMM5

(1310) 0x1b6f88 MOV	-0x8(%RCX),%R10

(1310) 0x1b6f8c VSUBPD	%YMM5,%YMM3,%YMM6

(1310) 0x1b6f90 VMOVUPD	%YMM6,(%RDI,%R10,8)

(1310) 0x1b6f96 MOV	-0x28(%RCX),%R10

(1310) 0x1b6f9a VADDPD	%YMM5,%YMM3,%YMM3

(1310) 0x1b6f9e VMOVUPD	%YMM3,(%RDI,%R10,8)

(1310) 0x1b6fa4 VADDPD	%YMM10,%YMM9,%YMM3

(1310) 0x1b6fa9 VMULPD	%YMM1,%YMM3,%YMM3

(1310) 0x1b6fad VADDPD	%YMM3,%YMM2,%YMM5

(1310) 0x1b6fb1 VSUBPD	%YMM3,%YMM2,%YMM2

(1310) 0x1b6fb5 VSUBPD	%YMM9,%YMM10,%YMM3

(1310) 0x1b6fba VMULPD	%YMM1,%YMM3,%YMM3

(1310) 0x1b6fbe VSUBPD	%YMM4,%YMM3,%YMM6

(1310) 0x1b6fc2 VXORPD	%YMM0,%YMM6,%YMM6

(1310) 0x1b6fc6 VSHUFPS	$0x4e,%YMM6,%YMM6,%YMM6

(1310) 0x1b6fcb VADDPD	%YMM3,%YMM4,%YMM3

(1310) 0x1b6fcf VXORPD	%YMM0,%YMM3,%YMM3

(1310) 0x1b6fd3 VSHUFPS	$0x4e,%YMM3,%YMM3,%YMM3

(1310) 0x1b6fd8 MOV	(%RCX),%R10

(1310) 0x1b6fdb VSUBPD	%YMM6,%YMM5,%YMM4

(1310) 0x1b6fdf VMOVUPD	%YMM4,(%RDI,%R10,8)

(1310) 0x1b6fe5 MOV	-0x20(%RCX),%R10

(1310) 0x1b6fe9 VADDPD	%YMM3,%YMM2,%YMM4

(1310) 0x1b6fed VMOVUPD	%YMM4,(%RDI,%R10,8)

(1310) 0x1b6ff3 MOV	-0x30(%RCX),%R10

(1310) 0x1b6ff7 VADDPD	%YMM6,%YMM5,%YMM4

(1310) 0x1b6ffb VMOVUPD	%YMM4,(%RDI,%R10,8)

(1310) 0x1b7001 MOV	-0x10(%RCX),%R10

(1310) 0x1b7005 VSUBPD	%YMM3,%YMM2,%YMM2

(1310) 0x1b7009 VMOVUPD	%YMM2,(%RDI,%R10,8)

(1310) 0x1b700f ADD	$0x2,%R8

(1310) 0x1b7013 ADD	%RAX,%RDI

(1310) 0x1b7016 ADD	$0xe0,%RDX

(1310) 0x1b701d ADD	%RSI,%RCX

(1310) 0x1b7020 CMP	%R9,%R8

(1310) 0x1b7023 JL	1b6e20

0x1b7029 POP	%RBX

0x1b702a POP	%RBP

0x1b702b VZEROUPPER

0x1b702e RET

Coverage (%)	Name	Source Location	Module
►99.99+	apply#0x296210	dftw-direct.c:51	bench
○	doit	fftw-bench.c:274	bench
○	speed		bench
○	bench_main	bench-main.c:91	bench
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		bench

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run run_0

Source file and lines	t1fv_8.c:141-202
Module	bench

The function is defined in:

/home/fmusial/FFTW_Benchmarks/fftw-3.3.10-clang/dft/simd/avx2/../../../simd-support/simd-avx2.h:85,252,280,315
/home/fmusial/FFTW_Benchmarks/fftw-3.3.10-clang/dft/simd/avx2/./../common/t1fv_8.c:141-202

Warnings:
get_cqa_results:

Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 2.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/fmusial/FFTW_Benchmarks/fftw-3.3.10-clang/dft/simd/avx2/./../common/t1fv_8.c:201

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes.

General properties

nb instructions	21
nb uops	24
loop length	86
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.50	2.50	3.00	3.00	2.00	2.50	2.50	3.00
cycles	2.50	2.50	3.00	3.00	2.00	2.50	2.50	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	3.00
Overall L1	6.00

Vectorization ratios

INT

all	33%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	28%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	16%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	16%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

5% of peak load performance is reached (6.67 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 3.00 cycles (2.00x speedup).

ASM code

In the binary file, the address of the function is: 1b6dd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
CMP %R9,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JGE 1b702b <t1fv_8+0x25b>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
PUSH %RBP	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.25	N/A
PUSH %RBX	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
MOV 0x10(%RBP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
IMUL $0x70,%R8,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
SAL $0x4,%RAX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
LEA 0x12ff77(%RIP),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV (%RSI),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADD %R10,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0xc0,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x38,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
SAL $0x3,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
VBROADCASTI128 0x115071(%RIP),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (25.0%)
VBROADCASTSD 0x1140b0(%RIP),%YMM1	1	0	0	0.50	0.50	0	0	0	0	5	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
POP %RBX	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %RBP	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0.33	0.33	0	0	1	0.33	0	1	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run run_0

Source file and lines	t1fv_8.c:141-202
Module	bench

The function is defined in:

/home/fmusial/FFTW_Benchmarks/fftw-3.3.10-clang/dft/simd/avx2/../../../simd-support/simd-avx2.h:85,252,280,315
/home/fmusial/FFTW_Benchmarks/fftw-3.3.10-clang/dft/simd/avx2/./../common/t1fv_8.c:141-202

Warnings:
get_cqa_results:

Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 2.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/fmusial/FFTW_Benchmarks/fftw-3.3.10-clang/dft/simd/avx2/./../common/t1fv_8.c:201

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes.

General properties

nb instructions	21
nb uops	24
loop length	86
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.50	2.50	3.00	3.00	2.00	2.50	2.50	3.00
cycles	2.50	2.50	3.00	3.00	2.00	2.50	2.50	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	3.00
Overall L1	6.00

Vectorization ratios

INT

all	33%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	28%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	16%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	16%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

5% of peak load performance is reached (6.67 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 1b6dd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
CMP %R9,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JGE 1b702b <t1fv_8+0x25b>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
PUSH %RBP	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.25	N/A
PUSH %RBX	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
MOV 0x10(%RBP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
IMUL $0x70,%R8,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
SAL $0x4,%RAX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
LEA 0x12ff77(%RIP),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV (%RSI),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADD %R10,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0xc0,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x38,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
SAL $0x3,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
VBROADCASTI128 0x115071(%RIP),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (25.0%)
VBROADCASTSD 0x1140b0(%RIP),%YMM1	1	0	0	0.50	0.50	0	0	0	0	5	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
POP %RBX	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %RBP	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0.33	0.33	0	0	1	0.33	0	1	N/A

Name	Coverage (%)	Time (s)
▼t1fv_8#0x1b6dd0–	25.82	86.75
○Loop 1310 - t1fv_8.c:141-196 - bench	25.81	86.73

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code