OV - FFTW ICX - Function t2fv

	Function: t2fv_8#0x53ed90	Module: bench	Source: t2fv_8.c:141-202 [...]	Coverage (incl. loops): 30.20% \| (excl. loops): 0.07%

/home/fmusial/FFTW_Benchmarks/fftw-3.3.10-icx/dft/simd/avx/./../common/t2fv_8.c: 141 - 202

--------------------------------------------------------------------------------

141: 	  for (m = mb, W = W + (mb * ((TWVL / VL) * 14)); m < me; m = m + VL, x = x + (VL * ms), W = W + (TWVL * 14), MAKE_VOLATILE_STRIDE(8, rs)) {

142: 	       V T4, Tq, Tm, Tr, T9, Tt, Te, Tu, T1, T3, T2;

143: 	       T1 = LD(&(x[0]), ms, &(x[0]));

144: 	       T2 = LD(&(x[WS(rs, 4)]), ms, &(x[0]));

145: 	       T3 = BYTWJ(&(W[TWVL * 6]), T2);

146: 	       T4 = VSUB(T1, T3);

147: 	       Tq = VADD(T1, T3);

148: 	       {

149: 		    V Tj, Tl, Ti, Tk;

150: 		    Ti = LD(&(x[WS(rs, 2)]), ms, &(x[0]));

151: 		    Tj = BYTWJ(&(W[TWVL * 2]), Ti);

152: 		    Tk = LD(&(x[WS(rs, 6)]), ms, &(x[0]));

153: 		    Tl = BYTWJ(&(W[TWVL * 10]), Tk);

154: 		    Tm = VSUB(Tj, Tl);

155: 		    Tr = VADD(Tj, Tl);

156: 	       }

157: 	       {

158: 		    V T6, T8, T5, T7;

159: 		    T5 = LD(&(x[WS(rs, 1)]), ms, &(x[WS(rs, 1)]));

160: 		    T6 = BYTWJ(&(W[0]), T5);

161: 		    T7 = LD(&(x[WS(rs, 5)]), ms, &(x[WS(rs, 1)]));

162: 		    T8 = BYTWJ(&(W[TWVL * 8]), T7);

163: 		    T9 = VSUB(T6, T8);

164: 		    Tt = VADD(T6, T8);

165: 	       }

166: 	       {

167: 		    V Tb, Td, Ta, Tc;

168: 		    Ta = LD(&(x[WS(rs, 7)]), ms, &(x[WS(rs, 1)]));

169: 		    Tb = BYTWJ(&(W[TWVL * 12]), Ta);

170: 		    Tc = LD(&(x[WS(rs, 3)]), ms, &(x[WS(rs, 1)]));

171: 		    Td = BYTWJ(&(W[TWVL * 4]), Tc);

172: 		    Te = VSUB(Tb, Td);

173: 		    Tu = VADD(Tb, Td);

174: 	       }

175: 	       {

176: 		    V Ts, Tv, Tw, Tx;

177: 		    Ts = VADD(Tq, Tr);

178: 		    Tv = VADD(Tt, Tu);

179: 		    ST(&(x[WS(rs, 4)]), VSUB(Ts, Tv), ms, &(x[0]));

180: 		    ST(&(x[0]), VADD(Ts, Tv), ms, &(x[0]));

181: 		    Tw = VSUB(Tq, Tr);

182: 		    Tx = VBYI(VSUB(Tu, Tt));

183: 		    ST(&(x[WS(rs, 6)]), VSUB(Tw, Tx), ms, &(x[0]));

184: 		    ST(&(x[WS(rs, 2)]), VADD(Tw, Tx), ms, &(x[0]));

185: 		    {

186: 			 V Tg, To, Tn, Tp, Tf, Th;

187: 			 Tf = VMUL(LDK(KP707106781), VADD(T9, Te));

188: 			 Tg = VADD(T4, Tf);

189: 			 To = VSUB(T4, Tf);

190: 			 Th = VMUL(LDK(KP707106781), VSUB(Te, T9));

191: 			 Tn = VBYI(VSUB(Th, Tm));

192: 			 Tp = VBYI(VADD(Tm, Th));

193: 			 ST(&(x[WS(rs, 7)]), VSUB(Tg, Tn), ms, &(x[WS(rs, 1)]));

194: 			 ST(&(x[WS(rs, 3)]), VADD(To, Tp), ms, &(x[WS(rs, 1)]));

195: 			 ST(&(x[WS(rs, 1)]), VADD(Tg, Tn), ms, &(x[WS(rs, 1)]));

196: 			 ST(&(x[WS(rs, 5)]), VSUB(To, Tp), ms, &(x[WS(rs, 1)]));

197: 		    }

198: 	       }

199: 	  }

200:      }

201:      VLEAVE();

202: }

/home/fmusial/FFTW_Benchmarks/fftw-3.3.10-icx/dft/simd/avx/../../../simd-support/simd-avx.h: 80 - 377

--------------------------------------------------------------------------------

80:      SUFF(_mm256_storeu_p)(x, v);

[...]

248:      return VSHUF(x, x,

[...]

278:      return VXOR(pmpm.v, x);

[...]

377:      return VFNMS(ti, si, VMUL(tr, sr));

0x53ed90 CMP	%R9,%R8

0x53ed93 JGE	53efa5

0x53ed99 PUSH	%RBP

0x53ed9a MOV	%RSP,%RBP

0x53ed9d PUSH	%RBX

0x53ed9e MOV	0x10(%RBP),%RAX

0x53eda2 MOV	0x1ac18f(%RIP),%RSI

0x53eda9 IMUL	$0xe0,%R8,%R10

0x53edb0 ADD	%R10,%RDX

0x53edb3 ADD	$0x1a0,%RDX

0x53edba ADD	$0x38,%RCX

0x53edbe SAL	$0x3,%RSI

0x53edc2 SAL	$0x4,%RAX

0x53edc6 VBROADCASTI128	0x173601(%RIP),%YMM0

0x53edcf VBROADCASTSD	0x1728e8(%RIP),%YMM1

0x53edd8 NOPL	(%RAX,%RAX,1)

(1427) 0x53ede0 VMOVUPD	(%RDI),%YMM2

(1427) 0x53ede4 MOV	-0x18(%RCX),%R10

(1427) 0x53ede8 VMOVUPD	(%RDI,%R10,8),%YMM3

(1427) 0x53edee VSHUFPD	$0x5,%YMM3,%YMM3,%YMM4

(1427) 0x53edf3 VMULPD	-0xc0(%RDX),%YMM4,%YMM4

(1427) 0x53edfb VFMSUB231PD	-0xe0(%RDX),%YMM3,%YMM4

(1427) 0x53ee04 VSUBPD	%YMM4,%YMM2,%YMM3

(1427) 0x53ee08 VADDPD	%YMM4,%YMM2,%YMM2

(1427) 0x53ee0c MOV	-0x28(%RCX),%R11

(1427) 0x53ee10 VMOVUPD	(%RDI,%R11,8),%YMM4

(1427) 0x53ee16 VSHUFPD	$0x5,%YMM4,%YMM4,%YMM5

(1427) 0x53ee1b VMULPD	-0x140(%RDX),%YMM5,%YMM5

(1427) 0x53ee23 MOV	-0x30(%RCX),%R11

(1427) 0x53ee27 VFMSUB231PD	-0x160(%RDX),%YMM4,%YMM5

(1427) 0x53ee30 MOV	-0x8(%RCX),%RBX

(1427) 0x53ee34 VMOVUPD	(%RDI,%RBX,8),%YMM4

(1427) 0x53ee39 VSHUFPD	$0x5,%YMM4,%YMM4,%YMM6

(1427) 0x53ee3e VMULPD	-0x40(%RDX),%YMM6,%YMM6

(1427) 0x53ee43 VFMSUB231PD	-0x60(%RDX),%YMM4,%YMM6

(1427) 0x53ee49 VSUBPD	%YMM6,%YMM5,%YMM4

(1427) 0x53ee4d VADDPD	%YMM6,%YMM5,%YMM5

(1427) 0x53ee51 VMOVUPD	(%RDI,%R11,8),%YMM6

(1427) 0x53ee57 VSHUFPD	$0x5,%YMM6,%YMM6,%YMM7

(1427) 0x53ee5c VMULPD	-0x180(%RDX),%YMM7,%YMM7

(1427) 0x53ee64 VFMSUB231PD	-0x1a0(%RDX),%YMM6,%YMM7

(1427) 0x53ee6d MOV	-0x10(%RCX),%R11

(1427) 0x53ee71 VMOVUPD	(%RDI,%R11,8),%YMM6

(1427) 0x53ee77 VSHUFPD	$0x5,%YMM6,%YMM6,%YMM8

(1427) 0x53ee7c VMULPD	-0x80(%RDX),%YMM8,%YMM8

(1427) 0x53ee81 VFMSUB231PD	-0xa0(%RDX),%YMM6,%YMM8

(1427) 0x53ee8a VSUBPD	%YMM8,%YMM7,%YMM6

(1427) 0x53ee8f VADDPD	%YMM7,%YMM8,%YMM7

(1427) 0x53ee93 MOV	(%RCX),%R11

(1427) 0x53ee96 VMOVUPD	(%RDI,%R11,8),%YMM8

(1427) 0x53ee9c VSHUFPD	$0x5,%YMM8,%YMM8,%YMM9

(1427) 0x53eea2 VMULPD	(%RDX),%YMM9,%YMM9

(1427) 0x53eea6 VFMSUB231PD	-0x20(%RDX),%YMM8,%YMM9

(1427) 0x53eeac MOV	-0x20(%RCX),%R11

(1427) 0x53eeb0 VMOVUPD	(%RDI,%R11,8),%YMM8

(1427) 0x53eeb6 VSHUFPD	$0x5,%YMM8,%YMM8,%YMM10

(1427) 0x53eebc VMULPD	-0x100(%RDX),%YMM10,%YMM10

(1427) 0x53eec4 VFMSUB231PD	-0x120(%RDX),%YMM8,%YMM10

(1427) 0x53eecd VSUBPD	%YMM10,%YMM9,%YMM8

(1427) 0x53eed2 VADDPD	%YMM10,%YMM9,%YMM9

(1427) 0x53eed7 VADDPD	%YMM5,%YMM2,%YMM10

(1427) 0x53eedb VADDPD	%YMM7,%YMM9,%YMM11

(1427) 0x53eedf VSUBPD	%YMM11,%YMM10,%YMM12

(1427) 0x53eee4 VMOVUPD	%YMM12,(%RDI,%R10,8)

(1427) 0x53eeea VADDPD	%YMM11,%YMM10,%YMM10

(1427) 0x53eeef VMOVUPD	%YMM10,(%RDI)

(1427) 0x53eef3 VSUBPD	%YMM5,%YMM2,%YMM2

(1427) 0x53eef7 VSUBPD	%YMM7,%YMM9,%YMM5

(1427) 0x53eefb VXORPD	%YMM0,%YMM5,%YMM5

(1427) 0x53eeff VSHUFPS	$0x4e,%YMM5,%YMM5,%YMM5

(1427) 0x53ef04 MOV	-0x8(%RCX),%R10

(1427) 0x53ef08 VSUBPD	%YMM5,%YMM2,%YMM7

(1427) 0x53ef0c VMOVUPD	%YMM7,(%RDI,%R10,8)

(1427) 0x53ef12 MOV	-0x28(%RCX),%R10

(1427) 0x53ef16 VADDPD	%YMM5,%YMM2,%YMM2

(1427) 0x53ef1a VMOVUPD	%YMM2,(%RDI,%R10,8)

(1427) 0x53ef20 VADDPD	%YMM6,%YMM8,%YMM2

(1427) 0x53ef24 VMULPD	%YMM1,%YMM2,%YMM2

(1427) 0x53ef28 VADDPD	%YMM2,%YMM3,%YMM5

(1427) 0x53ef2c VSUBPD	%YMM2,%YMM3,%YMM2

(1427) 0x53ef30 VSUBPD	%YMM6,%YMM8,%YMM3

(1427) 0x53ef34 VMULPD	%YMM1,%YMM3,%YMM3

(1427) 0x53ef38 VSUBPD	%YMM4,%YMM3,%YMM6

(1427) 0x53ef3c VXORPD	%YMM0,%YMM6,%YMM6

(1427) 0x53ef40 VSHUFPS	$0x4e,%YMM6,%YMM6,%YMM6

(1427) 0x53ef45 VADDPD	%YMM3,%YMM4,%YMM3

(1427) 0x53ef49 VXORPD	%YMM0,%YMM3,%YMM3

(1427) 0x53ef4d VSHUFPS	$0x4e,%YMM3,%YMM3,%YMM3

(1427) 0x53ef52 MOV	(%RCX),%R10

(1427) 0x53ef55 VSUBPD	%YMM6,%YMM5,%YMM4

(1427) 0x53ef59 VMOVUPD	%YMM4,(%RDI,%R10,8)

(1427) 0x53ef5f MOV	-0x20(%RCX),%R10

(1427) 0x53ef63 VADDPD	%YMM3,%YMM2,%YMM4

(1427) 0x53ef67 VMOVUPD	%YMM4,(%RDI,%R10,8)

(1427) 0x53ef6d MOV	-0x30(%RCX),%R10

(1427) 0x53ef71 VADDPD	%YMM6,%YMM5,%YMM4

(1427) 0x53ef75 VMOVUPD	%YMM4,(%RDI,%R10,8)

(1427) 0x53ef7b MOV	-0x10(%RCX),%R10

(1427) 0x53ef7f VSUBPD	%YMM3,%YMM2,%YMM2

(1427) 0x53ef83 VMOVUPD	%YMM2,(%RDI,%R10,8)

(1427) 0x53ef89 ADD	$0x2,%R8

(1427) 0x53ef8d ADD	$0x1c0,%RDX

(1427) 0x53ef94 ADD	%RSI,%RCX

(1427) 0x53ef97 ADD	%RAX,%RDI

(1427) 0x53ef9a CMP	%R9,%R8

(1427) 0x53ef9d JL	53ede0

0x53efa3 POP	%RBX

0x53efa4 POP	%RBP

0x53efa5 VZEROUPPER

0x53efa8 RET

Coverage (%)	Name	Source Location	Module
►12.60+	apply#0x667370	dftw-direct.c:51	bench
○	doit	fftw-bench.c:275	bench
○	speed		bench
○	bench_main	bench-main.c:86	bench
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		bench
►12.59+	apply#0x667370	dftw-direct.c:51	bench
○	doit	fftw-bench.c:275	bench
○	speed		bench
○	bench_main	bench-main.c:86	bench
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		bench
►12.53+	apply#0x667370	dftw-direct.c:51	bench
○	doit	fftw-bench.c:275	bench
○	speed		bench
○	bench_main	bench-main.c:86	bench
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		bench
►12.47+	apply#0x667370	dftw-direct.c:51	bench
○	doit	fftw-bench.c:275	bench
○	speed		bench
○	bench_main	bench-main.c:86	bench
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		bench
►12.47+	apply#0x667370	dftw-direct.c:51	bench
○	doit	fftw-bench.c:274	bench
○	speed		bench
○	bench_main	bench-main.c:86	bench
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		bench
►12.46+	apply#0x667370	dftw-direct.c:51	bench
○	doit	fftw-bench.c:275	bench
○	speed		bench
○	bench_main	bench-main.c:86	bench
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		bench
►12.46+	apply#0x667370	dftw-direct.c:51	bench
○	doit	fftw-bench.c:275	bench
○	speed		bench
○	bench_main	bench-main.c:86	bench
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		bench
►12.39+	apply#0x667370	dftw-direct.c:51	bench
○	doit	fftw-bench.c:275	bench
○	speed		bench
○	bench_main	bench-main.c:86	bench
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		bench

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.07% of application time for run run_0

Source file and lines	t2fv_8.c:141-202
Module	bench

The function is defined in:

/home/fmusial/FFTW_Benchmarks/fftw-3.3.10-icx/dft/simd/avx/./../common/t2fv_8.c:141-202
/home/fmusial/FFTW_Benchmarks/fftw-3.3.10-icx/dft/simd/avx/../../../simd-support/simd-avx.h:80,248,278,377

Warnings:
get_cqa_results:

Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.75 to 2.00 cycles (2.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/fmusial/FFTW_Benchmarks/fftw-3.3.10-icx/dft/simd/avx/./../common/t2fv_8.c:201

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes.

General properties

nb instructions	20
nb uops	23
loop length	86
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.75 cycles
front end	5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.25	2.25	3.00	3.00	2.00	2.25	2.25	3.00
cycles	2.25	2.25	3.00	3.00	2.00	2.25	2.25	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.75
Dispatch	3.00
Overall L1	5.75

Vectorization ratios

INT

all	25%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	22%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Vector efficiency ratios

INT

all	15%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	15%
load	16%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.75 cycles. At this rate:

5% of peak load performance is reached (6.96 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.75 to 3.00 cycles (1.92x speedup).

ASM code

In the binary file, the address of the function is: 53ed90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
CMP %R9,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JGE 53efa5 <t2fv_8+0x215>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
PUSH %RBP	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.25	N/A
PUSH %RBX	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
MOV 0x10(%RBP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x1ac18f(%RIP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
IMUL $0xe0,%R8,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %R10,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x1a0,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x38,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
SAL $0x3,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
SAL $0x4,%RAX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
VBROADCASTI128 0x173601(%RIP),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (25.0%)
VBROADCASTSD 0x1728e8(%RIP),%YMM1	1	0	0	0.50	0.50	0	0	0	0	5	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
POP %RBX	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %RBP	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0.33	0.33	0	0	1	0.33	0	1	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.07% of application time for run run_0

Source file and lines	t2fv_8.c:141-202
Module	bench

The function is defined in:

/home/fmusial/FFTW_Benchmarks/fftw-3.3.10-icx/dft/simd/avx/./../common/t2fv_8.c:141-202
/home/fmusial/FFTW_Benchmarks/fftw-3.3.10-icx/dft/simd/avx/../../../simd-support/simd-avx.h:80,248,278,377

Warnings:
get_cqa_results:

Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.75 to 2.00 cycles (2.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/fmusial/FFTW_Benchmarks/fftw-3.3.10-icx/dft/simd/avx/./../common/t2fv_8.c:201

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes.

General properties

nb instructions	20
nb uops	23
loop length	86
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.75 cycles
front end	5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.25	2.25	3.00	3.00	2.00	2.25	2.25	3.00
cycles	2.25	2.25	3.00	3.00	2.00	2.25	2.25	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.75
Dispatch	3.00
Overall L1	5.75

Vectorization ratios

INT

all	25%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	22%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Vector efficiency ratios

INT

all	15%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	15%
load	16%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.75 cycles. At this rate:

5% of peak load performance is reached (6.96 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 53ed90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
CMP %R9,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JGE 53efa5 <t2fv_8+0x215>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
PUSH %RBP	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.25	N/A
PUSH %RBX	1	0	0	0.33	0.33	1	0	0	0.33	3	1	N/A
MOV 0x10(%RBP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x1ac18f(%RIP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
IMUL $0xe0,%R8,%R10	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %R10,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x1a0,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x38,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
SAL $0x3,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
SAL $0x4,%RAX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
VBROADCASTI128 0x173601(%RIP),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (25.0%)
VBROADCASTSD 0x1728e8(%RIP),%YMM1	1	0	0	0.50	0.50	0	0	0	0	5	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
POP %RBX	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
POP %RBP	1	0	0	0.50	0.50	0	0	0	0	2	0.50	N/A
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0.33	0.33	0	0	1	0.33	0	1	N/A

Name	Coverage (%)	Time (s)
▼t2fv_8#0x53ed90–	30.20	83.15
○Loop 1427 - t2fv_8.c:141-196 - bench	30.12	82.94

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code